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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [top.v] - Diff between revs 2 and 6

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//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
 
// New project directory structure
 
//
//
//
 
 
// This top module is primarly used for testing plain PCI bridge core without any other cores attached.
// This top module is primarly used for testing plain PCI bridge core without any other cores attached.
// Other cores can be included in this top module and appropriate changes incorporated for overall design
// Other cores can be included in this top module and appropriate changes incorporated for overall design
 
`include "timescale.v"
 
 
module TOP
module TOP
(
(
    CLK,
    CLK,
    AD,
    AD,

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