OpenCores

Rev 35	Rev 62
Line 40...	Line 40...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2002/03/21 07:36:04 mihad`
	`// Files updated with missing includes, resolved some race conditions in test bench`
	`//`
`// Revision 1.3 2002/02/01 15:25:13 mihad`	`// Revision 1.3 2002/02/01 15:25:13 mihad`
`// Repaired a few bugs, updated specification, added test bench files and design document`	`// Repaired a few bugs, updated specification, added test bench files and design document`
`//`	`//`
`// Revision 1.2 2001/10/05 08:14:30 mihad`	`// Revision 1.2 2001/10/05 08:14:30 mihad`
`// Updated all files with inclusion of timescale file for simulation purposes.`	`// Updated all files with inclusion of timescale file for simulation purposes.`
Line 109...	Line 112...
`WE_O,`	`WE_O,`
`CAB_O,`	`CAB_O,`
`ACK_I,`	`ACK_I,`
`RTY_I,`	`RTY_I,`
`ERR_I`	`ERR_I`

	`ifdef PCI_BIST
	`,`
	`// debug chain signals`
	`SO ,`
	`SI ,`
	`shift_DR ,`
	`capture_DR ,`
	`extest ,`
	`tck`
	`endif
`);`	`);`

`input CLK ;`	`input CLK ;`
`inout [31:0] AD ;`	`inout [31:0] AD ;`
`inout [3:0] CBE ;`	`inout [3:0] CBE ;`
Line 161...	Line 175...
`output CAB_O ;`	`output CAB_O ;`
`input ACK_I ;`	`input ACK_I ;`
`input RTY_I ;`	`input RTY_I ;`
`input ERR_I ;`	`input ERR_I ;`

	`ifdef PCI_BIST
	`/*-----------------------------------------------------`
	`BIST debug chain port signals`
	`-----------------------------------------------------*/`
	`output SO ;`
	`input SI ;`
	`input shift_DR ;`
	`input capture_DR ;`
	`input extest ;`
	`input tck ;`

	`endif

`wire [31:0] AD_out ;`	`wire [31:0] AD_out ;`
`wire [31:0] AD_en ;`	`wire [31:0] AD_en ;`


Line 311...	Line 337...
`.PCI_PERRn_EN_OUT ( PERR_en ),`	`.PCI_PERRn_EN_OUT ( PERR_en ),`

`// system error pin`	`// system error pin`
`.PCI_SERRn_OUT ( SERR_out ),`	`.PCI_SERRn_OUT ( SERR_out ),`
`.PCI_SERRn_EN_OUT ( SERR_en )`	`.PCI_SERRn_EN_OUT ( SERR_en )`

	`ifdef PCI_BIST
	`,`
	`.SO (SO),`
	`.SI (SI),`
	`.shift_DR (shift_DR),`
	`.capture_DR (capture_DR),`
	`.extest (extest),`
	`.tck (tck)`
	`endif
`);`	`);`


`// PCI IO buffers instantiation`	`// PCI IO buffers instantiation`
`ifdef ACTIVE_LOW_OE	`ifdef ACTIVE_LOW_OE

Line 40...

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.4  2002/03/21 07:36:04  mihad

// Files updated with missing includes, resolved some race conditions in test bench

//

// Revision 1.3  2002/02/01 15:25:13  mihad

// Revision 1.3  2002/02/01 15:25:13  mihad

// Repaired a few bugs, updated specification, added test bench files and design document

// Repaired a few bugs, updated specification, added test bench files and design document

//

//

// Revision 1.2  2001/10/05 08:14:30  mihad

// Revision 1.2  2001/10/05 08:14:30  mihad

// Updated all files with inclusion of timescale file for simulation purposes.

// Updated all files with inclusion of timescale file for simulation purposes.

Line 109...

Line 112...

    WE_O,

    WE_O,

    CAB_O,

    CAB_O,

    ACK_I,

    ACK_I,

    RTY_I,

    RTY_I,

    ERR_I

    ERR_I

`ifdef PCI_BIST

    // debug chain signals

    SO         ,

    SI         ,

    shift_DR   ,

    capture_DR ,

    extest     ,

tck

`endif

);

);

input           CLK ;

input           CLK ;

inout   [31:0]  AD ;

inout   [31:0]  AD ;

inout   [3:0]   CBE ;

inout   [3:0]   CBE ;

Line 161...

Line 175...

output          CAB_O ;

output          CAB_O ;

input           ACK_I ;

input           ACK_I ;

input           RTY_I ;

input           RTY_I ;

input           ERR_I ;

input           ERR_I ;

`ifdef PCI_BIST

/*-----------------------------------------------------

BIST debug chain port signals

-----------------------------------------------------*/

output  SO ;

input   SI ;

input   shift_DR ;

input   capture_DR ;

input   extest ;

input   tck ;

`endif

wire    [31:0]  AD_out ;

wire    [31:0]  AD_out ;

wire    [31:0]  AD_en ;

wire    [31:0]  AD_en ;

Line 311...

Line 337...

    .PCI_PERRn_EN_OUT ( PERR_en ),

    .PCI_PERRn_EN_OUT ( PERR_en ),

    // system error pin

    // system error pin

    .PCI_SERRn_OUT ( SERR_out ),

    .PCI_SERRn_OUT ( SERR_out ),

    .PCI_SERRn_EN_OUT ( SERR_en )

    .PCI_SERRn_EN_OUT ( SERR_en )

`ifdef PCI_BIST

    .SO         (SO),

    .SI         (SI),

    .shift_DR   (shift_DR),

    .capture_DR (capture_DR),

    .extest     (extest),

    .tck        (tck)

`endif

);

);

// PCI IO buffers instantiation

// PCI IO buffers instantiation

`ifdef ACTIVE_LOW_OE

`ifdef ACTIVE_LOW_OE

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