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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [top.v] - Diff between revs 63 and 67

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Rev 63 Rev 67
Line 40... Line 40...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.6  2002/10/11 10:09:01  mihad
 
// Added additional testcase and changed rst name in BIST to trst
 
//
// Revision 1.5  2002/10/08 17:17:06  mihad
// Revision 1.5  2002/10/08 17:17:06  mihad
// Added BIST signals for RAMs.
// Added BIST signals for RAMs.
//
//
// Revision 1.4  2002/03/21 07:36:04  mihad
// Revision 1.4  2002/03/21 07:36:04  mihad
// Files updated with missing includes, resolved some race conditions in test bench
// Files updated with missing includes, resolved some race conditions in test bench
Line 119... Line 122...
    ERR_I
    ERR_I
 
 
`ifdef PCI_BIST
`ifdef PCI_BIST
    ,
    ,
    // debug chain signals
    // debug chain signals
    trst       ,
    scanb_rst,      // bist scan reset
    SO         ,
    scanb_clk,      // bist scan clock
    SI         ,
    scanb_si,       // bist scan serial in
    shift_DR   ,
    scanb_so,       // bist scan serial out
    capture_DR ,
    scanb_sen       // bist scan shift enable
    extest     ,
 
    tck
 
`endif
`endif
);
);
 
 
input           CLK ;
input           CLK ;
inout   [31:0]  AD ;
inout   [31:0]  AD ;
Line 183... Line 184...
 
 
`ifdef PCI_BIST
`ifdef PCI_BIST
/*-----------------------------------------------------
/*-----------------------------------------------------
BIST debug chain port signals
BIST debug chain port signals
-----------------------------------------------------*/
-----------------------------------------------------*/
input   trst ;
input   scanb_rst;      // bist scan reset
output  SO ;
input   scanb_clk;      // bist scan clock
input   SI ;
input   scanb_si;       // bist scan serial in
input   shift_DR ;
output  scanb_so;       // bist scan serial out
input   capture_DR ;
input   scanb_sen;      // bist scan shift enable
input   extest ;
 
input   tck ;
 
 
 
`endif
`endif
 
 
wire    [31:0]  AD_out ;
wire    [31:0]  AD_out ;
wire    [31:0]  AD_en ;
wire    [31:0]  AD_en ;
 
 
Line 345... Line 343...
    .PCI_SERRn_OUT ( SERR_out ),
    .PCI_SERRn_OUT ( SERR_out ),
    .PCI_SERRn_EN_OUT ( SERR_en )
    .PCI_SERRn_EN_OUT ( SERR_en )
 
 
`ifdef PCI_BIST
`ifdef PCI_BIST
    ,
    ,
    .trst       (trst),
    .scanb_rst      (scanb_rst),
    .SO         (SO),
    .scanb_clk      (scanb_clk),
    .SI         (SI),
    .scanb_si       (scanb_si),
    .shift_DR   (shift_DR),
    .scanb_so       (scanb_so),
    .capture_DR (capture_DR),
    .scanb_sen      (scanb_sen)
    .extest     (extest),
 
    .tck        (tck)
 
`endif
`endif
);
);
 
 
 
 
// PCI IO buffers instantiation
// PCI IO buffers instantiation

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