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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [top.v] - Diff between revs 67 and 68

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Rev 67 Rev 68
Line 40... Line 40...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.7  2002/10/17 22:49:22  tadejm
 
// Changed BIST signals for RAMs.
 
//
// Revision 1.6  2002/10/11 10:09:01  mihad
// Revision 1.6  2002/10/11 10:09:01  mihad
// Added additional testcase and changed rst name in BIST to trst
// Added additional testcase and changed rst name in BIST to trst
//
//
// Revision 1.5  2002/10/08 17:17:06  mihad
// Revision 1.5  2002/10/08 17:17:06  mihad
// Added BIST signals for RAMs.
// Added BIST signals for RAMs.
Line 126... Line 129...
    // debug chain signals
    // debug chain signals
    scanb_rst,      // bist scan reset
    scanb_rst,      // bist scan reset
    scanb_clk,      // bist scan clock
    scanb_clk,      // bist scan clock
    scanb_si,       // bist scan serial in
    scanb_si,       // bist scan serial in
    scanb_so,       // bist scan serial out
    scanb_so,       // bist scan serial out
    scanb_sen       // bist scan shift enable
    scanb_en        // bist scan shift enable
`endif
`endif
);
);
 
 
input           CLK ;
input           CLK ;
inout   [31:0]  AD ;
inout   [31:0]  AD ;
Line 188... Line 191...
-----------------------------------------------------*/
-----------------------------------------------------*/
input   scanb_rst;      // bist scan reset
input   scanb_rst;      // bist scan reset
input   scanb_clk;      // bist scan clock
input   scanb_clk;      // bist scan clock
input   scanb_si;       // bist scan serial in
input   scanb_si;       // bist scan serial in
output  scanb_so;       // bist scan serial out
output  scanb_so;       // bist scan serial out
input   scanb_sen;      // bist scan shift enable
input   scanb_en;       // bist scan shift enable
`endif
`endif
 
 
wire    [31:0]  AD_out ;
wire    [31:0]  AD_out ;
wire    [31:0]  AD_en ;
wire    [31:0]  AD_en ;
 
 
Line 347... Line 350...
    ,
    ,
    .scanb_rst      (scanb_rst),
    .scanb_rst      (scanb_rst),
    .scanb_clk      (scanb_clk),
    .scanb_clk      (scanb_clk),
    .scanb_si       (scanb_si),
    .scanb_si       (scanb_si),
    .scanb_so       (scanb_so),
    .scanb_so       (scanb_so),
    .scanb_sen      (scanb_sen)
    .scanb_en       (scanb_en)
`endif
`endif
);
);
 
 
 
 
// PCI IO buffers instantiation
// PCI IO buffers instantiation

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