| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2002/02/01 15:25:13 mihad
|
|
// Repaired a few bugs, updated specification, added test bench files and design document
|
|
//
|
// Revision 1.2 2001/10/05 08:14:30 mihad
|
// Revision 1.2 2001/10/05 08:14:30 mihad
|
// Updated all files with inclusion of timescale file for simulation purposes.
|
// Updated all files with inclusion of timescale file for simulation purposes.
|
//
|
//
|
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
|
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
|
// New project directory structure
|
// New project directory structure
|
| Line 68... |
Line 71... |
pci_tar_be,
|
pci_tar_be,
|
pci_tar_burst_ok,
|
pci_tar_burst_ok,
|
pci_cache_line_size,
|
pci_cache_line_size,
|
cache_lsize_not_zero,
|
cache_lsize_not_zero,
|
wb_read_done_out,
|
wb_read_done_out,
|
|
w_attempt,
|
|
|
pcir_fifo_wenable_out,
|
pcir_fifo_wenable_out,
|
pcir_fifo_data_out,
|
pcir_fifo_data_out,
|
pcir_fifo_be_out,
|
pcir_fifo_be_out,
|
pcir_fifo_control_out,
|
pcir_fifo_control_out,
|
//pcir_fifo_renable_out, for PCI Target !!!
|
//pcir_fifo_renable_out, for PCI Target !!!
|
//pcir_fifo_data_in, for PCI Target !!!
|
//pcir_fifo_data_in, for PCI Target !!!
|
//pcir_fifo_be_in, for PCI Target !!!
|
//pcir_fifo_be_in, for PCI Target !!!
|
//pcir_fifo_control_in, for PCI Target !!!
|
//pcir_fifo_control_in, for PCI Target !!!
|
//pcir_fifo_flush_out, for PCI Target !!!
|
//pcir_fifo_flush_out, for PCI Target !!!
|
pcir_fifo_almost_full_in,
|
|
pcir_fifo_full_in,
|
|
//pcir_fifo_almost_empty_in, for PCI Target !!!
|
//pcir_fifo_almost_empty_in, for PCI Target !!!
|
//pcir_fifo_empty_in, NOT used
|
//pcir_fifo_empty_in, NOT used
|
//pcir_fifo_transaction_ready_in, NOT used
|
//pcir_fifo_transaction_ready_in, NOT used
|
//pciw_fifo_wenable_out, for PCI Target !!!
|
//pciw_fifo_wenable_out, for PCI Target !!!
|
//pciw_fifo_addr_data_out, for PCI Target !!!
|
//pciw_fifo_addr_data_out, for PCI Target !!!
|
| Line 146... |
Line 148... |
input [3:0] pci_tar_be ; // byte enables for requested read from PCI Target
|
input [3:0] pci_tar_be ; // byte enables for requested read from PCI Target
|
input pci_tar_burst_ok ;
|
input pci_tar_burst_ok ;
|
input [7:0] pci_cache_line_size ; // CACHE line size register value for burst length
|
input [7:0] pci_cache_line_size ; // CACHE line size register value for burst length
|
input cache_lsize_not_zero ;
|
input cache_lsize_not_zero ;
|
output wb_read_done_out ; // read done and PCIR_FIFO has data ready
|
output wb_read_done_out ; // read done and PCIR_FIFO has data ready
|
|
output w_attempt ;
|
|
|
reg wb_read_done_out ;
|
reg wb_read_done_out ;
|
reg wb_read_done ;
|
reg wb_read_done ;
|
|
|
/*----------------------------------------------------------------------------------------------------------------------
|
/*----------------------------------------------------------------------------------------------------------------------
|
| Line 157... |
Line 160... |
---------------------------------------------------------------------------------------------------------------------*/
|
---------------------------------------------------------------------------------------------------------------------*/
|
output pcir_fifo_wenable_out ; // PCIR_FIFO write enable output
|
output pcir_fifo_wenable_out ; // PCIR_FIFO write enable output
|
output [31:0] pcir_fifo_data_out ; // data output to PCIR_FIFO
|
output [31:0] pcir_fifo_data_out ; // data output to PCIR_FIFO
|
output [3:0] pcir_fifo_be_out ; // byte enable output to PCIR_FIFO
|
output [3:0] pcir_fifo_be_out ; // byte enable output to PCIR_FIFO
|
output [3:0] pcir_fifo_control_out ; // control bus output to PCIR_FIFO
|
output [3:0] pcir_fifo_control_out ; // control bus output to PCIR_FIFO
|
input pcir_fifo_almost_full_in ; // almost full status indicator from PCIR_FIFO
|
|
input pcir_fifo_full_in ; // full status indicator from PCIR_FIFO
|
|
|
|
reg [31:0] pcir_fifo_data_out ;
|
reg [31:0] pcir_fifo_data_out ;
|
reg pcir_fifo_wenable_out ;
|
reg pcir_fifo_wenable_out ;
|
reg pcir_fifo_wenable ;
|
reg pcir_fifo_wenable ;
|
reg [3:0] pcir_fifo_control_out ;
|
reg [3:0] pcir_fifo_control_out ;
|
| Line 226... |
Line 227... |
LOGIC, COUNTERS, STATE MACHINE and some control register bits
|
LOGIC, COUNTERS, STATE MACHINE and some control register bits
|
=============================================================
|
=============================================================
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
###########################################################################################################*/
|
###########################################################################################################*/
|
|
|
|
reg last_data_transferred ; // signal is set by STATE MACHINE after each complete transfere !
|
|
|
// wire for write attempt - 1 when PCI Target attempt to write and PCIW_FIFO has a write transaction ready
|
// wire for write attempt - 1 when PCI Target attempt to write and PCIW_FIFO has a write transaction ready
|
wire w_attempt = ( pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in ) ;
|
`ifdef REGISTER_WBM_OUTPUTS
|
|
reg w_attempt;
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if (reset_in)
|
|
w_attempt <= #`FF_DELAY 1'b0;
|
|
else
|
|
begin
|
|
if (pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in)
|
|
w_attempt <= #`FF_DELAY 1'b1;
|
|
else
|
|
if (last_data_transferred)
|
|
w_attempt <= #`FF_DELAY 1'b0;
|
|
end
|
|
end
|
|
`else
|
|
assign w_attempt = ( pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in ) ;
|
|
`endif
|
|
|
// wire for read attempt - 1 when PCI Target is attempting a read and PCIR_FIFO is not full !
|
// wire for read attempt - 1 when PCI Target is attempting a read and PCIR_FIFO is not full !
|
// because of transaction ordering, PCI Master must not start read untill all writes are done -> at that
|
// because of transaction ordering, PCI Master must not start read untill all writes are done -> at that
|
// moment PCIW_FIFO is empty !!! (when read is pending PCI Target will block new reads and writes)
|
// moment PCIW_FIFO is empty !!! (when read is pending PCI Target will block new reads and writes)
|
wire r_attempt = ( pci_tar_read_request && ~pcir_fifo_full_in && pciw_fifo_empty_in ) ;
|
wire r_attempt = ( pci_tar_read_request && !w_attempt);// pciw_fifo_empty_in ) ;
|
|
|
// Signal is used for reads on WB, when there is retry!
|
// Signal is used for reads on WB, when there is retry!
|
reg first_wb_data_access ;
|
reg first_wb_data_access ;
|
|
|
reg last_data_from_pciw_fifo ; // signal tells when there is last data in pciw_fifo
|
reg last_data_from_pciw_fifo ; // signal tells when there is last data in pciw_fifo
|
| Line 250... |
Line 270... |
last_data_from_pciw_fifo <= 1'b1 ; // signal for last data from PCIW_FIFO
|
last_data_from_pciw_fifo <= 1'b1 ; // signal for last data from PCIW_FIFO
|
else
|
else
|
last_data_from_pciw_fifo <= 1'b0 ;
|
last_data_from_pciw_fifo <= 1'b0 ;
|
end
|
end
|
|
|
|
|
reg read_count_load;
|
reg read_count_load;
|
reg read_count_enable;
|
reg read_count_enable;
|
|
|
reg [(`PCIR_ADDR_LENGTH - 1):0] max_read_count ;
|
reg [(`PCIR_ADDR_LENGTH - 1):0] max_read_count ;
|
always@(pci_cache_line_size or cache_lsize_not_zero or pci_tar_cmd)
|
always@(pci_cache_line_size or cache_lsize_not_zero or pci_tar_cmd)
|
| Line 271... |
Line 290... |
|
|
reg [(`PCIR_ADDR_LENGTH - 1):0] read_count ;
|
reg [(`PCIR_ADDR_LENGTH - 1):0] read_count ;
|
|
|
// cache line bound indicator - it signals when data for one complete cacheline was read
|
// cache line bound indicator - it signals when data for one complete cacheline was read
|
wire read_bound_comb = ~|( { read_count[(`PCIR_ADDR_LENGTH - 1):2], read_count[0] } ) ;
|
wire read_bound_comb = ~|( { read_count[(`PCIR_ADDR_LENGTH - 1):2], read_count[0] } ) ;
|
|
|
reg read_bound ;
|
reg read_bound ;
|
always@(posedge wb_clock_in or posedge reset_in)
|
always@(posedge wb_clock_in or posedge reset_in)
|
begin
|
begin
|
if ( reset_in )
|
if ( reset_in )
|
read_bound <= #`FF_DELAY 1'b0 ;
|
read_bound <= #`FF_DELAY 1'b0 ;
|
| Line 295... |
Line 315... |
else
|
else
|
if (read_count_enable)
|
if (read_count_enable)
|
read_count <= #`FF_DELAY read_count - 1'b1 ;
|
read_count <= #`FF_DELAY read_count - 1'b1 ;
|
end
|
end
|
|
|
|
|
|
|
wire [7:0] cache_line_wire ; // wire assigned directly from cache_line register !!!
|
|
// Logic used in State Machine logic implemented out of State Machine because of less delay!
|
// Logic used in State Machine logic implemented out of State Machine because of less delay!
|
// definition of signal telling, when there is last data written into FIFO
|
// definition of signal telling, when there is last data written into FIFO
|
always@(pci_tar_cmd or pci_tar_burst_ok or read_bound or pcir_fifo_almost_full_in)
|
always@(pci_tar_cmd or pci_tar_burst_ok or read_bound)
|
begin
|
begin
|
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
|
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
|
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) -> pci_tar_burst_ok
|
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) -> pci_tar_burst_ok
|
case ({pci_tar_cmd, pci_tar_burst_ok})
|
case ({pci_tar_cmd, pci_tar_burst_ok})
|
{`BC_MEM_READ, 1'b1},
|
{`BC_MEM_READ, 1'b1},
|
{`BC_MEM_READ_LN, 1'b1} :
|
{`BC_MEM_READ_LN, 1'b1} :
|
begin // when burst cycle
|
begin // when burst cycle
|
if (/*(cache_line_wire == 8'h1) || pcir_fifo_almost_full_in*/ read_bound)
|
if (read_bound)
|
last_data_to_pcir_fifo <= 1'b1 ;
|
last_data_to_pcir_fifo <= 1'b1 ;
|
else
|
else
|
last_data_to_pcir_fifo <= 1'b0 ;
|
last_data_to_pcir_fifo <= 1'b0 ;
|
end
|
end
|
{`BC_MEM_READ_MUL, 1'b1} :
|
{`BC_MEM_READ_MUL, 1'b1} :
|
begin // when burst cycle
|
begin // when burst cycle
|
if (pcir_fifo_almost_full_in)
|
if (read_bound)
|
last_data_to_pcir_fifo <= 1'b1 ;
|
last_data_to_pcir_fifo <= 1'b1 ;
|
else
|
else
|
last_data_to_pcir_fifo <= 1'b0 ;
|
last_data_to_pcir_fifo <= 1'b0 ;
|
end
|
end
|
default :
|
default :
|
| Line 371... |
Line 388... |
wire retry = RTY_I || set_retry ; // retry signal - logic OR function between RTY_I and internal WB no response retry!
|
wire retry = RTY_I || set_retry ; // retry signal - logic OR function between RTY_I and internal WB no response retry!
|
reg [7:0] rty_counter ; // output from retry counter
|
reg [7:0] rty_counter ; // output from retry counter
|
reg [7:0] rty_counter_in ; // input value - output value + 1 OR output value
|
reg [7:0] rty_counter_in ; // input value - output value + 1 OR output value
|
reg rty_counter_max_value ; // signal tells when retry counter riches maximum value!
|
reg rty_counter_max_value ; // signal tells when retry counter riches maximum value!
|
reg reset_rty_cnt ; // signal for asynchronous reset of retry counter after each complete transfere
|
reg reset_rty_cnt ; // signal for asynchronous reset of retry counter after each complete transfere
|
reg last_data_transferred ; // signal is set by STATE MACHINE after each complete transfere !
|
|
|
|
// sinchronous signal after each transfere and asynchronous signal 'reset_rty_cnt' after reset
|
// sinchronous signal after each transfere and asynchronous signal 'reset_rty_cnt' after reset
|
// for reseting the retry counter
|
// for reseting the retry counter
|
always@(posedge reset_in or posedge wb_clock_in)
|
always@(posedge reset_in or posedge wb_clock_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
reset_rty_cnt <= 1'b1 ; // asynchronous set when reset signal is active
|
reset_rty_cnt <= 1'b1 ; // asynchronous set when reset signal is active
|
else
|
else
|
reset_rty_cnt <= ACK_I || ERR_I ; // synchronous set after completed transfere
|
reset_rty_cnt <= ACK_I || ERR_I || last_data_transferred ; // synchronous set after completed transfere
|
end
|
end
|
|
|
// Retry counter register control
|
// Retry counter register control
|
always@(posedge reset_in or posedge wb_clock_in)
|
always@(posedge reset_in or posedge wb_clock_in)
|
begin
|
begin
|
| Line 411... |
Line 427... |
rty_counter_in <= rty_counter + 1'b1 ; // count up
|
rty_counter_in <= rty_counter + 1'b1 ; // count up
|
rty_counter_max_value <= 1'b0 ;
|
rty_counter_max_value <= 1'b0 ;
|
end
|
end
|
end
|
end
|
|
|
reg [7:0] cache_line ; // output from cache line down-counter
|
/*reg [7:0] cache_line ; // output from cache line down-counter
|
reg [7:0] cache_line_in ; // input to cache line counter
|
reg [7:0] cache_line_in ; // input to cache line counter
|
reg cache_line_into_cnt ; // control signal for loading cache line size to counter
|
reg cache_line_into_cnt ; // control signal for loading cache line size to counter
|
reg cache_line_count ; // control signal for count enable
|
reg cache_line_count ; // control signal for count enable
|
reg cache_line_reg_used ; // if pci_cache_line_size is ZERO then all PCIR_FIFO is read
|
reg cache_line_reg_used ; // if pci_cache_line_size is ZERO then all PCIR_FIFO is read
|
|
|
assign cache_line_wire = cache_line ;
|
assign cache_line_wire = cache_line ;
|
// cache line size down-counter register control
|
// cache line size down-counter register control
|
always@(posedge wb_clock_in or posedge reset_in)
|
always@(posedge wb_clock_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in) // reset counter
|
if (reset_in) // reset counter
|
cache_line <= #`FF_DELAY 8'h00 ;
|
cache_line <= #`FF_DELAY 8'h00 ;
|
else
|
else
|
cache_line <= #`FF_DELAY cache_line_in ; // count down or hold value depending on cache line counter logic
|
cache_line <= #`FF_DELAY cache_line_in ; // count down or hold value depending on cache line counter logic
|
end
|
end
|
// cache line size down-counter logic
|
// cache line size down-counter logic
|
always@(cache_line_into_cnt or cache_line_count or pci_cache_line_size or cache_lsize_not_zero or cache_line)
|
always@(cache_line_into_cnt or cache_line_count or pci_cache_line_size or cache_lsize_not_zero or cache_line)
|
begin
|
begin
|
if (cache_line_into_cnt) // load cache line size into counter
|
if (cache_line_into_cnt) // load cache line size into counter
|
begin
|
begin
|
if (cache_lsize_not_zero)
|
if (cache_lsize_not_zero)
|
cache_line_in = pci_cache_line_size ;
|
cache_line_in = pci_cache_line_size ;
|
else
|
else
|
cache_line_in = 8'h01 ;
|
cache_line_in = 8'h01 ;
|
end
|
end
|
else
|
else
|
if (cache_line_count)
|
if (cache_line_count)
|
begin
|
begin
|
cache_line_in = cache_line - 1'h1 ; // count down
|
cache_line_in = cache_line - 1'h1 ; // count down
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cache_line_in = cache_line ;
|
cache_line_in = cache_line ;
|
end
|
end
|
end
|
end
|
|
*/
|
|
|
|
|
reg [31:0] addr_cnt_out ; // output value from address counter to WB ADDRESS output
|
reg [31:0] addr_cnt_out ; // output value from address counter to WB ADDRESS output
|
reg [31:0] addr_cnt_in ; // input address value to address counter
|
reg [31:0] addr_cnt_in ; // input address value to address counter
|
reg addr_into_cnt ; // control signal for loading starting address into counter
|
reg addr_into_cnt ; // control signal for loading starting address into counter
|
| Line 507... |
Line 523... |
reg wb_we_o ; // Internal signal for driwing WE_O on WB bus
|
reg wb_we_o ; // Internal signal for driwing WE_O on WB bus
|
reg wb_cyc_o ; // Internal signal for driwing CYC_O on WB bus and for enableing burst signal generation
|
reg wb_cyc_o ; // Internal signal for driwing CYC_O on WB bus and for enableing burst signal generation
|
|
|
reg retried ; // Signal is output value from FF and is set for one clock period after retried_d is set
|
reg retried ; // Signal is output value from FF and is set for one clock period after retried_d is set
|
reg retried_d ; // Signal is set whenever cycle is retried and is input to FF for delaying -> used in S_IDLE state
|
reg retried_d ; // Signal is set whenever cycle is retried and is input to FF for delaying -> used in S_IDLE state
|
|
reg retried_write;
|
|
reg rty_i_delayed; // Dignal used for determinig the source of retry!
|
|
|
reg first_data_is_burst ; // Signal is set in S_WRITE or S_READ states, when data transfere is burst!
|
reg first_data_is_burst ; // Signal is set in S_WRITE or S_READ states, when data transfere is burst!
|
reg first_data_is_burst_reg ;
|
reg first_data_is_burst_reg ;
|
wire burst_transfer ; // This signal is set when data transfere is burst and is reset with RESET or last data transfered
|
wire burst_transfer ; // This signal is set when data transfere is burst and is reset with RESET or last data transfered
|
|
|
| Line 519... |
Line 537... |
always@(posedge wb_clock_in or posedge reset_in)
|
always@(posedge wb_clock_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in) // reset signals
|
if (reset_in) // reset signals
|
begin
|
begin
|
retried <= #`FF_DELAY 1'b0 ;
|
retried <= #`FF_DELAY 1'b0 ;
|
|
retried_write <= #`FF_DELAY 1'b0 ;
|
|
rty_i_delayed <= #`FF_DELAY 1'B0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
retried <= #`FF_DELAY retried_d ; // delaying retried signal
|
retried <= #`FF_DELAY retried_d ; // delaying retried signal
|
|
retried_write <= #`FF_DELAY retried ;
|
|
rty_i_delayed <= #`FF_DELAY RTY_I ;
|
end
|
end
|
end
|
end
|
|
|
// Determinig if first data is a part of BURST or just a single transfere!
|
// Determinig if first data is a part of BURST or just a single transfere!
|
always@(addr_into_cnt or r_attempt or pci_tar_burst_ok or max_read_count or
|
always@(addr_into_cnt or r_attempt or pci_tar_burst_ok or max_read_count or
|
| Line 587... |
Line 609... |
RTY_I or
|
RTY_I or
|
ERR_I or
|
ERR_I or
|
w_attempt or
|
w_attempt or
|
r_attempt or
|
r_attempt or
|
retried or
|
retried or
|
|
rty_i_delayed or
|
pci_tar_read_request or
|
pci_tar_read_request or
|
rty_counter_max_value or
|
rty_counter_max_value or
|
last_data_to_pcir_fifo or
|
last_data_to_pcir_fifo or
|
first_wb_data_access or
|
first_wb_data_access or
|
last_data_from_pciw_fifo_reg
|
last_data_from_pciw_fifo_reg
|
| Line 607... |
Line 630... |
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out <= 1'b0 ;
|
error_source_out <= 1'b0 ;
|
error_source_out <= 1'b0 ;
|
retried_d <= 1'b0 ;
|
retried_d <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
case ({w_attempt, r_attempt, retried})
|
case ({w_attempt, r_attempt, retried})
|
3'b101 : // Write request for PCIW_FIFO to WB bus transaction
|
3'b101 : // Write request for PCIW_FIFO to WB bus transaction
|
begin // If there was retry, the same transaction must be initiated
|
begin // If there was retry, the same transaction must be initiated
|
pciw_fifo_renable <= 1'b0 ; // the same data
|
pciw_fifo_renable <= 1'b0 ; // the same data
|
addr_into_cnt <= 1'b0 ; // the same address
|
addr_into_cnt <= 1'b0 ; // the same address
|
read_count_load <= 1'b0 ; // no need for cache line when there is write
|
read_count_load <= 1'b0 ; // no need for cache line when there is write
|
|
if (rty_counter_max_value) // If retry counter reached maximum value
|
|
begin
|
|
n_state <= S_WRITE_ERR_RTY ;
|
|
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
|
|
error_source_out <= rty_i_delayed;
|
|
pci_error_sig_out <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
n_state <= S_WRITE ;
|
n_state <= S_WRITE ;
|
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
|
end
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
end
|
end
|
3'b100 : // Write request for PCIW_FIFO to WB bus transaction
|
3'b100 : // Write request for PCIW_FIFO to WB bus transaction
|
begin // If there is new transaction
|
begin // If there is new transaction
|
pciw_fifo_renable <= 1'b1 ; // first location is address (in FIFO), next will be data
|
pciw_fifo_renable <= 1'b1 ; // first location is address (in FIFO), next will be data
|
addr_into_cnt <= 1'b1 ; // address must be latched into address counter
|
addr_into_cnt <= 1'b1 ; // address must be latched into address counter
|
read_count_load <= 1'b0 ; // no need for cache line when there is write
|
read_count_load <= 1'b0 ; // no need for cache line when there is write
|
n_state <= S_WRITE ;
|
n_state <= S_WRITE ;
|
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
end
|
end
|
3'b011 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
3'b011 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
begin // If there was retry, the same transaction must be initiated
|
begin // If there was retry, the same transaction must be initiated
|
addr_into_cnt <= 1'b0 ; // the same address
|
addr_into_cnt <= 1'b0 ; // the same address
|
read_count_load <= 1'b0 ; // cache line counter must not be changed for retried read
|
read_count_load <= 1'b0 ; // cache line counter must not be changed for retried read
|
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
|
if (rty_counter_max_value) // If retry counter reached maximum value
|
|
begin
|
|
n_state <= S_READ_RTY;
|
|
read_rty_cnt_exp_out <= 1'b1 ; // signal for reporting read counter expired
|
|
end
|
|
else
|
|
begin
|
n_state <= S_READ ;
|
n_state <= S_READ ;
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
|
end
|
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
end
|
end
|
3'b010 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
3'b010 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
begin // If there is new transaction
|
begin // If there is new transaction
|
addr_into_cnt <= 1'b1 ; // address must be latched into counter from separate request bus
|
addr_into_cnt <= 1'b1 ; // address must be latched into counter from separate request bus
|
read_count_load <= 1'b1 ; // cache line size must be latched into its counter
|
read_count_load <= 1'b1 ; // cache line size must be latched into its counter
|
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
n_state <= S_READ ;
|
n_state <= S_READ ;
|
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
end
|
end
|
default : // stay in IDLE state
|
default : // stay in IDLE state
|
begin
|
begin
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable <= 1'b0 ;
|
addr_into_cnt <= 1'b0 ;
|
addr_into_cnt <= 1'b0 ;
|
read_count_load <= 1'b0 ;
|
read_count_load <= 1'b0 ;
|
n_state <= S_IDLE ;
|
n_state <= S_IDLE ;
|
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
end
|
end
|
endcase
|
endcase
|
wb_stb_o <= 1'b0 ;
|
wb_stb_o <= 1'b0 ;
|
wb_we_o <= 1'b0 ;
|
wb_we_o <= 1'b0 ;
|
wb_cyc_o <= 1'b0 ;
|
wb_cyc_o <= 1'b0 ;
|
| Line 834... |
Line 893... |
addr_count <= 1'b0 ;
|
addr_count <= 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
case ({first_wb_data_access, rty_counter_max_value})
|
case ({first_wb_data_access, rty_counter_max_value})
|
2'b10 :
|
2'b10 :
|
begin
|
begin // if first data of the cycle (CYC_O) is retried - after each retry CYC_O goes inactive
|
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
|
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
|
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
retried_d <= 1'b1 ; // there was a retry
|
retried_d <= 1'b1 ; // there was a retry
|
end
|
end
|
2'b11 :
|
2'b11 :
|
begin
|
begin // if retry counter reached maximum value
|
n_state <= S_READ_RTY ; // go here to wait for PCI Target to remove read request
|
n_state <= S_READ_RTY ; // go here to wait for PCI Target to remove read request
|
read_rty_cnt_exp_out <= 1'b1 ; // signal for reporting read counter expired
|
read_rty_cnt_exp_out <= 1'b1 ; // signal for reporting read counter expired
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
retried_d <= 1'b1 ; // there was a retry
|
retried_d <= 1'b1 ; // there was a retry
|
end
|
end
|
default :
|
default : // if retry occures after at least 1 data was transferred without breaking cycle (CYC_O inactive)
|
begin
|
begin // then PCI device will retry access!
|
n_state <= S_TURN_ARROUND ; // go to S_TURN_ARROUND state
|
n_state <= S_TURN_ARROUND ; // go to S_TURN_ARROUND state
|
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired
|
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired
|
last_data_transferred <= 1'b1 ;
|
last_data_transferred <= 1'b1 ;
|
wb_read_done <= 1'b1 ;
|
wb_read_done <= 1'b1 ;
|
retried_d <= 1'b0 ; // retry must not be retried, since there is not a first data
|
retried_d <= 1'b0 ; // retry must not be retried, since there is not a first data
|
| Line 1036... |
Line 1095... |
end
|
end
|
else
|
else
|
begin
|
begin
|
if (wb_cyc_o)
|
if (wb_cyc_o)
|
begin
|
begin
|
CYC_O <= ~((ACK_I || RTY_I || ERR_I) && last_data_transferred) ;
|
CYC_O <= ~((ACK_I || RTY_I || ERR_I) && (last_data_transferred || retried_d)) ;
|
CAB_O <= ~((ACK_I || RTY_I || ERR_I) && last_data_transferred) && burst_transfer ;
|
CAB_O <= ~((ACK_I || RTY_I || ERR_I) && (last_data_transferred || retried_d)) && burst_transfer ;
|
STB_O <= ~((ACK_I || RTY_I || ERR_I) && last_data_transferred) ;
|
STB_O <= ~((ACK_I || RTY_I || ERR_I) && (last_data_transferred || retried_d)) ;
|
end
|
end
|
WE_O <= wb_we_o ;
|
WE_O <= wb_we_o ;
|
if (((wb_cyc_o && ~wb_cyc_reg) || ACK_I) && wb_we_o)
|
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
|
MDATA_O <= pciw_fifo_addr_data_in ;
|
MDATA_O <= pciw_fifo_addr_data_in ;
|
if ((wb_cyc_o && ~wb_cyc_reg) || ACK_I)
|
if ((wb_cyc_o && ~wb_cyc_reg) || ACK_I)
|
SEL_O <= wb_sel_o ;
|
SEL_O <= wb_sel_o ;
|
wb_cyc_reg <= wb_cyc_o ;
|
wb_cyc_reg <= wb_cyc_o ;
|
wb_read_done_out <= wb_read_done ;
|
wb_read_done_out <= wb_read_done ;
|
pcir_fifo_data_out <= MDATA_I ;
|
pcir_fifo_data_out <= MDATA_I ;
|
pcir_fifo_wenable_out <= pcir_fifo_wenable ;
|
pcir_fifo_wenable_out <= pcir_fifo_wenable ;
|
pcir_fifo_control_out <= pcir_fifo_control ;
|
pcir_fifo_control_out <= pcir_fifo_control ;
|
end
|
end
|
end
|
end
|
always@(pciw_fifo_renable or last_data_from_pciw_fifo_reg or wb_cyc_o or wb_cyc_reg or wb_we_o or
|
always@(pciw_fifo_renable or last_data_from_pciw_fifo_reg or wb_cyc_o or wb_cyc_reg or wb_we_o or retried_write or
|
pciw_fifo_control_in or pciw_fifo_empty_in)
|
pciw_fifo_control_in or pciw_fifo_empty_in)
|
begin
|
begin
|
pciw_fifo_renable_out <= (pciw_fifo_renable && ~wb_cyc_o) ||
|
pciw_fifo_renable_out <= (pciw_fifo_renable && ~wb_cyc_o) ||
|
(pciw_fifo_renable && ~last_data_from_pciw_fifo_reg) ||
|
(pciw_fifo_renable && ~last_data_from_pciw_fifo_reg) ||
|
(wb_cyc_o && ~wb_cyc_reg && wb_we_o) ;
|
(wb_cyc_o && ~wb_cyc_reg && wb_we_o && !retried_write) ;
|
last_data_from_pciw_fifo_reg <= pciw_fifo_control_in[`ADDR_CTRL_BIT] || pciw_fifo_empty_in ;
|
last_data_from_pciw_fifo_reg <= pciw_fifo_control_in[`ADDR_CTRL_BIT] || pciw_fifo_empty_in ;
|
end
|
end
|
`else
|
`else
|
always@(wb_cyc_o or wb_stb_o or wb_we_o or burst_transfer or pciw_fifo_addr_data_in or wb_sel_o or
|
always@(wb_cyc_o or wb_stb_o or wb_we_o or burst_transfer or pciw_fifo_addr_data_in or wb_sel_o or
|
wb_read_done or MDATA_I or pcir_fifo_wenable or pcir_fifo_control)
|
wb_read_done or MDATA_I or pcir_fifo_wenable or pcir_fifo_control)
|
