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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_master.v] - Diff between revs 2 and 6

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//
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// CVS Revision History
// CVS Revision History
//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
 
// New project directory structure
 
//
//
//
 
 
`define FSM_BITS 3 // number of bits needed for FSM states
`define FSM_BITS 3 // number of bits needed for FSM states
 
 
 
 
`include "bus_commands.v"
`include "bus_commands.v"
`include "constants.v"
`include "constants.v"
 
`include "timescale.v"
 
 
module WB_MASTER (  wb_clock_in,                // CLK_I
module WB_MASTER (  wb_clock_in,                // CLK_I
                    reset_in,                   // RST_I
                    reset_in,                   // RST_I
 
 
                    pci_tar_read_request,
                    pci_tar_read_request,

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