| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/03/05 11:53:47 mihad
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// Added some testcases, removed un-needed fifo signals
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//
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Modified testbench and fixed some bugs
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// Modified testbench and fixed some bugs
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//
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//
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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| Line 268... |
Line 271... |
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// Logic used in State Machine logic implemented out of State Machine because of less delay!
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// Logic used in State Machine logic implemented out of State Machine because of less delay!
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always@(pciw_fifo_control_in or pciw_fifo_almost_empty_in)
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always@(pciw_fifo_control_in or pciw_fifo_almost_empty_in)
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begin
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begin
|
if (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in) // if last data is going to be transfered
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if (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in) // if last data is going to be transfered
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last_data_from_pciw_fifo <= 1'b1 ; // signal for last data from PCIW_FIFO
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last_data_from_pciw_fifo = 1'b1 ; // signal for last data from PCIW_FIFO
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else
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else
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last_data_from_pciw_fifo <= 1'b0 ;
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last_data_from_pciw_fifo = 1'b0 ;
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end
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end
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reg read_count_load;
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reg read_count_load;
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reg read_count_enable;
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reg read_count_enable;
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| Line 329... |
Line 332... |
case ({pci_tar_cmd, pci_tar_burst_ok})
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case ({pci_tar_cmd, pci_tar_burst_ok})
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{`BC_MEM_READ, 1'b1},
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{`BC_MEM_READ, 1'b1},
|
{`BC_MEM_READ_LN, 1'b1} :
|
{`BC_MEM_READ_LN, 1'b1} :
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begin // when burst cycle
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begin // when burst cycle
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if (read_bound)
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if (read_bound)
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last_data_to_pcir_fifo <= 1'b1 ;
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last_data_to_pcir_fifo = 1'b1 ;
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else
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else
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last_data_to_pcir_fifo <= 1'b0 ;
|
last_data_to_pcir_fifo = 1'b0 ;
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end
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end
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{`BC_MEM_READ_MUL, 1'b1} :
|
{`BC_MEM_READ_MUL, 1'b1} :
|
begin // when burst cycle
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begin // when burst cycle
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if (read_bound)
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if (read_bound)
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last_data_to_pcir_fifo <= 1'b1 ;
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last_data_to_pcir_fifo = 1'b1 ;
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else
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else
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last_data_to_pcir_fifo <= 1'b0 ;
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last_data_to_pcir_fifo = 1'b0 ;
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end
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end
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default :
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default :
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// {`BC_IO_READ, 1'b0},
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// {`BC_IO_READ, 1'b0},
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// {`BC_IO_READ, 1'b1},
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// {`BC_IO_READ, 1'b1},
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// {`BC_MEM_READ, 1'b0},
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// {`BC_MEM_READ, 1'b0},
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// {`BC_MEM_READ_LN, 1'b0},
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// {`BC_MEM_READ_LN, 1'b0},
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// {`BC_MEM_READ_MUL, 1'b0}:
|
// {`BC_MEM_READ_MUL, 1'b0}:
|
begin // when single cycle
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begin // when single cycle
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last_data_to_pcir_fifo <= 1'b1 ;
|
last_data_to_pcir_fifo = 1'b1 ;
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end
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end
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endcase
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endcase
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end
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end
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|
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reg [3:0] wb_no_response_cnt ;
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reg [3:0] wb_no_response_cnt ;
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| Line 370... |
Line 373... |
// internal WB no response retry generator logic
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// internal WB no response retry generator logic
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always@(wait_for_wb_response or wb_no_response_cnt)
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always@(wait_for_wb_response or wb_no_response_cnt)
|
begin
|
begin
|
if (wb_no_response_cnt == 4'h8) // when there isn't response for 8 clocks, set internal retry
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if (wb_no_response_cnt == 4'h8) // when there isn't response for 8 clocks, set internal retry
|
begin
|
begin
|
wb_response_value <= 4'h0 ;
|
wb_response_value = 4'h0 ;
|
set_retry <= 1'b1 ;
|
set_retry = 1'b1 ;
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end
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end
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else
|
else
|
begin
|
begin
|
if (wait_for_wb_response)
|
if (wait_for_wb_response)
|
wb_response_value <= wb_no_response_cnt + 1'h1 ; // count clocks when no response
|
wb_response_value = wb_no_response_cnt + 1'h1 ; // count clocks when no response
|
else
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else
|
wb_response_value <= 4'h0 ;
|
wb_response_value = 4'h0 ;
|
set_retry <= 1'b0 ;
|
set_retry = 1'b0 ;
|
end
|
end
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end
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end
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|
|
wire retry = RTY_I || set_retry ; // retry signal - logic OR function between RTY_I and internal WB no response retry!
|
wire retry = RTY_I || set_retry ; // retry signal - logic OR function between RTY_I and internal WB no response retry!
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reg [7:0] rty_counter ; // output from retry counter
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reg [7:0] rty_counter ; // output from retry counter
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| Line 394... |
Line 397... |
// sinchronous signal after each transfere and asynchronous signal 'reset_rty_cnt' after reset
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// sinchronous signal after each transfere and asynchronous signal 'reset_rty_cnt' after reset
|
// for reseting the retry counter
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// for reseting the retry counter
|
always@(posedge reset_in or posedge wb_clock_in)
|
always@(posedge reset_in or posedge wb_clock_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
reset_rty_cnt <= 1'b1 ; // asynchronous set when reset signal is active
|
reset_rty_cnt <= #`FF_DELAY 1'b1 ; // asynchronous set when reset signal is active
|
else
|
else
|
reset_rty_cnt <= ACK_I || ERR_I || last_data_transferred ; // synchronous set after completed transfere
|
reset_rty_cnt <= #`FF_DELAY ACK_I || ERR_I || last_data_transferred ; // synchronous set after completed transfere
|
end
|
end
|
|
|
// Retry counter register control
|
// Retry counter register control
|
always@(posedge reset_in or posedge wb_clock_in)
|
always@(posedge reset_in or posedge wb_clock_in)
|
begin
|
begin
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| Line 417... |
Line 420... |
// Retry counter logic
|
// Retry counter logic
|
always@(rty_counter)
|
always@(rty_counter)
|
begin
|
begin
|
if(rty_counter == `WB_RTY_CNT_MAX - 1'b1) // stop counting
|
if(rty_counter == `WB_RTY_CNT_MAX - 1'b1) // stop counting
|
begin
|
begin
|
rty_counter_in <= rty_counter ;
|
rty_counter_in = rty_counter ;
|
rty_counter_almost_max_value <= 1'b1 ;
|
rty_counter_almost_max_value = 1'b1 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rty_counter_in <= rty_counter + 1'b1 ; // count up
|
rty_counter_in = rty_counter + 1'b1 ; // count up
|
rty_counter_almost_max_value <= 1'b0 ;
|
rty_counter_almost_max_value = 1'b0 ;
|
end
|
end
|
end
|
end
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|
|
reg [31:0] addr_cnt_out ; // output value from address counter to WB ADDRESS output
|
reg [31:0] addr_cnt_out ; // output value from address counter to WB ADDRESS output
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reg [31:0] addr_cnt_in ; // input address value to address counter
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reg [31:0] addr_cnt_in ; // input address value to address counter
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| Line 521... |
Line 524... |
if (r_attempt)
|
if (r_attempt)
|
begin
|
begin
|
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
|
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
|
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) -> pci_tar_burst_ok
|
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) -> pci_tar_burst_ok
|
if (pci_tar_burst_ok && (max_read_count != 8'h1))
|
if (pci_tar_burst_ok && (max_read_count != 8'h1))
|
first_data_is_burst <= 1'b1 ;
|
first_data_is_burst = 1'b1 ;
|
else
|
else
|
first_data_is_burst <= 1'b0 ;
|
first_data_is_burst = 1'b0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
first_data_is_burst <= 1'b0 ;
|
first_data_is_burst = 1'b0 ;
|
end
|
end
|
end
|
end
|
else
|
else
|
first_data_is_burst <= pciw_fifo_control_in[`BURST_BIT] && ~pciw_fifo_empty_in ;
|
first_data_is_burst = pciw_fifo_control_in[`BURST_BIT] && ~pciw_fifo_empty_in ;
|
end
|
end
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|
|
// FF for seting and reseting burst_transfer signal
|
// FF for seting and reseting burst_transfer signal
|
always@(posedge wb_clock_in or posedge reset_in)
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always@(posedge wb_clock_in or posedge reset_in)
|
begin
|
begin
|
| Line 584... |
Line 587... |
begin
|
begin
|
case (c_state)
|
case (c_state)
|
S_IDLE:
|
S_IDLE:
|
begin
|
begin
|
// Default values for signals not used in this state
|
// Default values for signals not used in this state
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable = 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control = 4'h0 ;
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addr_count <= 1'b0 ;
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addr_count = 1'b0 ;
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read_count_enable <= 1'b0 ;
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read_count_enable = 1'b0 ;
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pci_error_sig_out <= 1'b0 ;
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pci_error_sig_out = 1'b0 ;
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error_source_out <= 1'b0 ;
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error_source_out = 1'b0 ;
|
retried_d <= 1'b0 ;
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retried_d = 1'b0 ;
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last_data_transferred <= 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done = 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
write_rty_cnt_exp_out = 1'b0 ;
|
error_source_out <= 1'b0 ;
|
error_source_out = 1'b0 ;
|
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out = 1'b0 ;
|
read_rty_cnt_exp_out <= 1'b0 ;
|
read_rty_cnt_exp_out = 1'b0 ;
|
case ({w_attempt, r_attempt, retried})
|
case ({w_attempt, r_attempt, retried})
|
3'b101 : // Write request for PCIW_FIFO to WB bus transaction
|
3'b101 : // Write request for PCIW_FIFO to WB bus transaction
|
begin // If there was retry, the same transaction must be initiated
|
begin // If there was retry, the same transaction must be initiated
|
pciw_fifo_renable <= 1'b0 ; // the same data
|
pciw_fifo_renable = 1'b0 ; // the same data
|
addr_into_cnt <= 1'b0 ; // the same address
|
addr_into_cnt = 1'b0 ; // the same address
|
read_count_load <= 1'b0 ; // no need for cache line when there is write
|
read_count_load = 1'b0 ; // no need for cache line when there is write
|
n_state <= S_WRITE ;
|
n_state = S_WRITE ;
|
end
|
end
|
3'b100 : // Write request for PCIW_FIFO to WB bus transaction
|
3'b100 : // Write request for PCIW_FIFO to WB bus transaction
|
begin // If there is new transaction
|
begin // If there is new transaction
|
pciw_fifo_renable <= 1'b1 ; // first location is address (in FIFO), next will be data
|
pciw_fifo_renable = 1'b1 ; // first location is address (in FIFO), next will be data
|
addr_into_cnt <= 1'b1 ; // address must be latched into address counter
|
addr_into_cnt = 1'b1 ; // address must be latched into address counter
|
read_count_load <= 1'b0 ; // no need for cache line when there is write
|
read_count_load = 1'b0 ; // no need for cache line when there is write
|
n_state <= S_WRITE ;
|
n_state = S_WRITE ;
|
end
|
end
|
3'b011 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
3'b011 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
begin // If there was retry, the same transaction must be initiated
|
begin // If there was retry, the same transaction must be initiated
|
addr_into_cnt <= 1'b0 ; // the same address
|
addr_into_cnt = 1'b0 ; // the same address
|
read_count_load <= 1'b0 ; // cache line counter must not be changed for retried read
|
read_count_load = 1'b0 ; // cache line counter must not be changed for retried read
|
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
pciw_fifo_renable = 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
n_state <= S_READ ;
|
n_state = S_READ ;
|
end
|
end
|
3'b010 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
3'b010 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
begin // If there is new transaction
|
begin // If there is new transaction
|
addr_into_cnt <= 1'b1 ; // address must be latched into counter from separate request bus
|
addr_into_cnt = 1'b1 ; // address must be latched into counter from separate request bus
|
read_count_load <= 1'b1 ; // cache line size must be latched into its counter
|
read_count_load = 1'b1 ; // cache line size must be latched into its counter
|
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
pciw_fifo_renable = 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
n_state <= S_READ ;
|
n_state = S_READ ;
|
end
|
end
|
default : // stay in IDLE state
|
default : // stay in IDLE state
|
begin
|
begin
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable = 1'b0 ;
|
addr_into_cnt <= 1'b0 ;
|
addr_into_cnt = 1'b0 ;
|
read_count_load <= 1'b0 ;
|
read_count_load = 1'b0 ;
|
n_state <= S_IDLE ;
|
n_state = S_IDLE ;
|
end
|
end
|
endcase
|
endcase
|
wb_stb_o <= 1'b0 ;
|
wb_stb_o = 1'b0 ;
|
wb_we_o <= 1'b0 ;
|
wb_we_o = 1'b0 ;
|
wb_cyc_o <= 1'b0 ;
|
wb_cyc_o = 1'b0 ;
|
end
|
end
|
S_WRITE: // WRITE from PCIW_FIFO to WB bus
|
S_WRITE: // WRITE from PCIW_FIFO to WB bus
|
begin
|
begin
|
// Default values for signals not used in this state
|
// Default values for signals not used in this state
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable = 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control = 4'h0 ;
|
addr_into_cnt <= 1'b0 ;
|
addr_into_cnt = 1'b0 ;
|
read_count_load <= 1'b0 ;
|
read_count_load = 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_count_enable = 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done = 1'b0 ;
|
read_rty_cnt_exp_out <= 1'b0 ;
|
read_rty_cnt_exp_out = 1'b0 ;
|
case ({ACK_I, ERR_I, RTY_I})
|
case ({ACK_I, ERR_I, RTY_I})
|
3'b100 : // If writting of one data is acknowledged
|
3'b100 : // If writting of one data is acknowledged
|
begin
|
begin
|
pciw_fifo_renable <= 1'b1 ; // prepare next value (address when new trans., data when burst tran.)
|
pciw_fifo_renable = 1'b1 ; // prepare next value (address when new trans., data when burst tran.)
|
addr_count <= 1'b1 ; // prepare next address if there will be burst
|
addr_count = 1'b1 ; // prepare next address if there will be burst
|
pci_error_sig_out <= 1'b0 ; // there was no error
|
pci_error_sig_out = 1'b0 ; // there was no error
|
error_source_out <= 1'b0 ;
|
error_source_out = 1'b0 ;
|
retried_d <= 1'b0 ; // there was no retry
|
retried_d = 1'b0 ; // there was no retry
|
write_rty_cnt_exp_out <= 1'b0 ; // there was no retry
|
write_rty_cnt_exp_out = 1'b0 ; // there was no retry
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
if (last_data_from_pciw_fifo_reg) // if last data was transfered
|
if (last_data_from_pciw_fifo_reg) // if last data was transfered
|
begin
|
begin
|
n_state <= S_IDLE ;
|
n_state = S_IDLE ;
|
last_data_transferred <= 1'b1 ; // signal for last data transfered
|
last_data_transferred = 1'b1 ; // signal for last data transfered
|
end
|
end
|
else
|
else
|
begin
|
begin
|
n_state <= S_WRITE ;
|
n_state = S_WRITE ;
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
end
|
end
|
end
|
end
|
3'b010 : // If writting of one data is terminated with ERROR
|
3'b010 : // If writting of one data is terminated with ERROR
|
begin
|
begin
|
pciw_fifo_renable <= 1'b1 ; // prepare next value (address when new trans., data when cleaning FIFO)
|
pciw_fifo_renable = 1'b1 ; // prepare next value (address when new trans., data when cleaning FIFO)
|
addr_count <= 1'b0 ; // no need for new address
|
addr_count = 1'b0 ; // no need for new address
|
retried_d <= 1'b0 ; // there was no retry
|
retried_d = 1'b0 ; // there was no retry
|
last_data_transferred <= 1'b1 ; // signal for last data transfered
|
last_data_transferred = 1'b1 ; // signal for last data transfered
|
pci_error_sig_out <= 1'b1 ; // segnal for error reporting
|
pci_error_sig_out = 1'b1 ; // segnal for error reporting
|
error_source_out <= 1'b0 ; // error source from other side of WB bus
|
error_source_out = 1'b0 ; // error source from other side of WB bus
|
write_rty_cnt_exp_out <= 1'b0 ; // there was no retry
|
write_rty_cnt_exp_out = 1'b0 ; // there was no retry
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
if (last_data_from_pciw_fifo_reg) // if last data was transfered
|
if (last_data_from_pciw_fifo_reg) // if last data was transfered
|
n_state <= S_IDLE ; // go to S_IDLE for new transfere
|
n_state = S_IDLE ; // go to S_IDLE for new transfere
|
else // if there wasn't last data of transfere
|
else // if there wasn't last data of transfere
|
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
n_state = S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
end
|
end
|
3'b001 : // If writting of one data is retried
|
3'b001 : // If writting of one data is retried
|
begin
|
begin
|
addr_count <= 1'b0 ;
|
addr_count = 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
retried_d <= 1'b1 ; // there was a retry
|
retried_d = 1'b1 ; // there was a retry
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
if(rty_counter_almost_max_value) // If retry counter reached maximum allowed value
|
if(rty_counter_almost_max_value) // If retry counter reached maximum allowed value
|
begin
|
begin
|
if (last_data_from_pciw_fifo_reg) // if last data was transfered
|
if (last_data_from_pciw_fifo_reg) // if last data was transfered
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable = 1'b0 ;
|
else // if there wasn't last data of transfere
|
else // if there wasn't last data of transfere
|
pciw_fifo_renable <= 1'b1 ;
|
pciw_fifo_renable = 1'b1 ;
|
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
n_state = S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
|
write_rty_cnt_exp_out = 1'b1 ; // signal for reporting write counter expired
|
pci_error_sig_out <= 1'b1 ;
|
pci_error_sig_out = 1'b1 ;
|
error_source_out <= 1'b1 ; // error ocuerd because of retry counter
|
error_source_out = 1'b1 ; // error ocuerd because of retry counter
|
end
|
end
|
else
|
else
|
begin
|
begin
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable = 1'b0 ;
|
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
|
n_state = S_IDLE ; // go to S_IDLE state for retrying the transaction
|
write_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
write_rty_cnt_exp_out = 1'b0 ; // retry counter hasn't expired yet
|
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out = 1'b0 ;
|
error_source_out <= 1'b0 ;
|
error_source_out = 1'b0 ;
|
end
|
end
|
end
|
end
|
default :
|
default :
|
begin
|
begin
|
addr_count <= 1'b0 ;
|
addr_count = 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
wait_for_wb_response <= 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
|
wait_for_wb_response = 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
|
error_source_out <= 1'b0 ; // if error ocures, error source is from other WB bus side
|
error_source_out = 1'b0 ; // if error ocures, error source is from other WB bus side
|
if((rty_counter_almost_max_value)&&(set_retry)) // when no WB response and RTY CNT reached maximum allowed value
|
if((rty_counter_almost_max_value)&&(set_retry)) // when no WB response and RTY CNT reached maximum allowed value
|
begin
|
begin
|
retried_d <= 1'b1 ;
|
retried_d = 1'b1 ;
|
if (last_data_from_pciw_fifo_reg) // if last data was transfered
|
if (last_data_from_pciw_fifo_reg) // if last data was transfered
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable = 1'b0 ;
|
else // if there wasn't last data of transfere
|
else // if there wasn't last data of transfere
|
pciw_fifo_renable <= 1'b1 ;
|
pciw_fifo_renable = 1'b1 ;
|
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
n_state = S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
|
write_rty_cnt_exp_out = 1'b1 ; // signal for reporting write counter expired
|
pci_error_sig_out <= 1'b1 ; // signal for error reporting
|
pci_error_sig_out = 1'b1 ; // signal for error reporting
|
end
|
end
|
else
|
else
|
begin
|
begin
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable = 1'b0 ;
|
retried_d <= 1'b0 ;
|
retried_d = 1'b0 ;
|
n_state <= S_WRITE ; // stay in S_WRITE state to wait WB to response
|
n_state = S_WRITE ; // stay in S_WRITE state to wait WB to response
|
write_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
write_rty_cnt_exp_out = 1'b0 ; // retry counter hasn't expired yet
|
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out = 1'b0 ;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
wb_stb_o <= 1'b1 ;
|
wb_stb_o = 1'b1 ;
|
wb_we_o <= 1'b1 ;
|
wb_we_o = 1'b1 ;
|
wb_cyc_o <= 1'b1 ;
|
wb_cyc_o = 1'b1 ;
|
end
|
end
|
S_WRITE_ERR_RTY: // Clean current write transaction from PCIW_FIFO if ERROR or Retry counter expired occures
|
S_WRITE_ERR_RTY: // Clean current write transaction from PCIW_FIFO if ERROR or Retry counter expired occures
|
begin
|
begin
|
`ifdef REGISTER_WBM_OUTPUTS
|
`ifdef REGISTER_WBM_OUTPUTS
|
pciw_fifo_renable <= !last_data_from_pciw_fifo_reg ; // put out next data (untill last data or FIFO empty)
|
pciw_fifo_renable = !last_data_from_pciw_fifo_reg ; // put out next data (untill last data or FIFO empty)
|
`else
|
`else
|
pciw_fifo_renable <= 1'b1 ; // put out next data (untill last data or FIFO empty)
|
pciw_fifo_renable = 1'b1 ; // put out next data (untill last data or FIFO empty)
|
`endif
|
`endif
|
last_data_transferred <= 1'b1 ; // after exiting this state, negedge of this signal is used
|
last_data_transferred = 1'b1 ; // after exiting this state, negedge of this signal is used
|
// Default values for signals not used in this state
|
// Default values for signals not used in this state
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable = 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control = 4'h0 ;
|
addr_into_cnt <= 1'b0 ;
|
addr_into_cnt = 1'b0 ;
|
read_count_load <= 1'b0 ;
|
read_count_load = 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_count_enable = 1'b0 ;
|
addr_count <= 1'b0 ;
|
addr_count = 1'b0 ;
|
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out = 1'b0 ;
|
error_source_out <= 1'b0 ;
|
error_source_out = 1'b0 ;
|
retried_d <= 1'b0 ;
|
retried_d = 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done = 1'b0 ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
write_rty_cnt_exp_out = 1'b0 ;
|
read_rty_cnt_exp_out <= 1'b0 ;
|
read_rty_cnt_exp_out = 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
// If last data is cleaned out from PCIW_FIFO
|
// If last data is cleaned out from PCIW_FIFO
|
if (last_data_from_pciw_fifo_reg)
|
if (last_data_from_pciw_fifo_reg)
|
n_state <= S_IDLE ;
|
n_state = S_IDLE ;
|
else
|
else
|
n_state <= S_WRITE_ERR_RTY ; // Clean until last data is cleaned out from FIFO
|
n_state = S_WRITE_ERR_RTY ; // Clean until last data is cleaned out from FIFO
|
wb_stb_o <= 1'b0 ;
|
wb_stb_o = 1'b0 ;
|
wb_we_o <= 1'b0 ;
|
wb_we_o = 1'b0 ;
|
wb_cyc_o <= 1'b0 ;
|
wb_cyc_o = 1'b0 ;
|
end
|
end
|
S_READ: // READ from WB bus to PCIR_FIFO
|
S_READ: // READ from WB bus to PCIR_FIFO
|
begin
|
begin
|
// Default values for signals not used in this state
|
// Default values for signals not used in this state
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable = 1'b0 ;
|
addr_into_cnt <= 1'b0 ;
|
addr_into_cnt = 1'b0 ;
|
read_count_load <= 1'b0 ;
|
read_count_load = 1'b0 ;
|
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out = 1'b0 ;
|
error_source_out <= 1'b0 ;
|
error_source_out = 1'b0 ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
write_rty_cnt_exp_out = 1'b0 ;
|
case ({ACK_I, ERR_I, RTY_I})
|
case ({ACK_I, ERR_I, RTY_I})
|
3'b100 : // If reading of one data is acknowledged
|
3'b100 : // If reading of one data is acknowledged
|
begin
|
begin
|
pcir_fifo_wenable <= 1'b1 ; // enable writting data into PCIR_FIFO
|
pcir_fifo_wenable = 1'b1 ; // enable writting data into PCIR_FIFO
|
addr_count <= 1'b1 ; // prepare next address if there will be burst
|
addr_count = 1'b1 ; // prepare next address if there will be burst
|
read_count_enable <= 1'b1 ; // decrease counter value for cache line size
|
read_count_enable = 1'b1 ; // decrease counter value for cache line size
|
retried_d <= 1'b0 ; // there was no retry
|
retried_d = 1'b0 ; // there was no retry
|
read_rty_cnt_exp_out <= 1'b0 ; // there was no retry
|
read_rty_cnt_exp_out = 1'b0 ; // there was no retry
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
// if last data was transfered
|
// if last data was transfered
|
if (last_data_to_pcir_fifo)
|
if (last_data_to_pcir_fifo)
|
begin
|
begin
|
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b1 ; // FIFO must indicate LAST data transfered
|
pcir_fifo_control[`LAST_CTRL_BIT] = 1'b1 ; // FIFO must indicate LAST data transfered
|
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
|
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`UNUSED_CTRL_BIT] = 1'b0 ;
|
pcir_fifo_control[`ADDR_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ;
|
last_data_transferred <= 1'b1 ; // signal for last data transfered
|
last_data_transferred = 1'b1 ; // signal for last data transfered
|
wb_read_done <= 1'b1 ; // signal last data of read transaction for PCI Target
|
wb_read_done = 1'b1 ; // signal last data of read transaction for PCI Target
|
n_state <= S_TURN_ARROUND ;
|
n_state = S_TURN_ARROUND ;
|
end
|
end
|
else // if not last data transfered
|
else // if not last data transfered
|
begin
|
begin
|
pcir_fifo_control <= 4'h0 ; // ZERO for control code
|
pcir_fifo_control = 4'h0 ; // ZERO for control code
|
last_data_transferred <= 1'b0 ; // not last data transfered
|
last_data_transferred = 1'b0 ; // not last data transfered
|
wb_read_done <= 1'b0 ; // read is not done yet
|
wb_read_done = 1'b0 ; // read is not done yet
|
n_state <= S_READ ;
|
n_state = S_READ ;
|
end
|
end
|
end
|
end
|
3'b010 : // If reading of one data is terminated with ERROR
|
3'b010 : // If reading of one data is terminated with ERROR
|
begin
|
begin
|
pcir_fifo_wenable <= 1'b1 ; // enable for writting to FIFO data with ERROR
|
pcir_fifo_wenable = 1'b1 ; // enable for writting to FIFO data with ERROR
|
addr_count <= 1'b0 ; // no need for new address
|
addr_count = 1'b0 ; // no need for new address
|
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`LAST_CTRL_BIT] = 1'b0 ;
|
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b1 ; // FIFO must indicate the DATA with ERROR
|
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b1 ; // FIFO must indicate the DATA with ERROR
|
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`UNUSED_CTRL_BIT] = 1'b0 ;
|
pcir_fifo_control[`ADDR_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ;
|
last_data_transferred <= 1'b1 ; // signal for last data transfered
|
last_data_transferred = 1'b1 ; // signal for last data transfered
|
wb_read_done <= 1'b1 ; // signal last data of read transaction for PCI Target
|
wb_read_done = 1'b1 ; // signal last data of read transaction for PCI Target
|
read_count_enable <= 1'b0 ; // no need for cache line, when error occures
|
read_count_enable = 1'b0 ; // no need for cache line, when error occures
|
n_state <= S_TURN_ARROUND ;
|
n_state = S_TURN_ARROUND ;
|
retried_d <= 1'b0 ; // there was no retry
|
retried_d = 1'b0 ; // there was no retry
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
read_rty_cnt_exp_out <= 1'b0 ; // there was no retry
|
read_rty_cnt_exp_out = 1'b0 ; // there was no retry
|
end
|
end
|
3'b001 : // If reading of one data is retried
|
3'b001 : // If reading of one data is retried
|
begin
|
begin
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable = 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control = 4'h0 ;
|
addr_count <= 1'b0 ;
|
addr_count = 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_count_enable = 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
case ({first_wb_data_access, rty_counter_almost_max_value})
|
case ({first_wb_data_access, rty_counter_almost_max_value})
|
2'b10 :
|
2'b10 :
|
begin // if first data of the cycle (CYC_O) is retried - after each retry CYC_O goes inactive
|
begin // if first data of the cycle (CYC_O) is retried - after each retry CYC_O goes inactive
|
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
|
n_state = S_IDLE ; // go to S_IDLE state for retrying the transaction
|
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
read_rty_cnt_exp_out = 1'b0 ; // retry counter hasn't expired yet
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done = 1'b0 ;
|
retried_d <= 1'b1 ; // there was a retry
|
retried_d = 1'b1 ; // there was a retry
|
end
|
end
|
2'b11 :
|
2'b11 :
|
begin // if retry counter reached maximum value
|
begin // if retry counter reached maximum value
|
n_state <= S_READ_RTY ; // go here to wait for PCI Target to remove read request
|
n_state = S_READ_RTY ; // go here to wait for PCI Target to remove read request
|
read_rty_cnt_exp_out <= 1'b1 ; // signal for reporting read counter expired
|
read_rty_cnt_exp_out = 1'b1 ; // signal for reporting read counter expired
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done = 1'b0 ;
|
retried_d <= 1'b1 ; // there was a retry
|
retried_d = 1'b1 ; // there was a retry
|
end
|
end
|
default : // if retry occures after at least 1 data was transferred without breaking cycle (CYC_O inactive)
|
default : // if retry occures after at least 1 data was transferred without breaking cycle (CYC_O inactive)
|
begin // then PCI device will retry access!
|
begin // then PCI device will retry access!
|
n_state <= S_TURN_ARROUND ; // go to S_TURN_ARROUND state
|
n_state = S_TURN_ARROUND ; // go to S_TURN_ARROUND state
|
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired
|
read_rty_cnt_exp_out = 1'b0 ; // retry counter hasn't expired
|
last_data_transferred <= 1'b1 ;
|
last_data_transferred = 1'b1 ;
|
wb_read_done <= 1'b1 ;
|
wb_read_done = 1'b1 ;
|
retried_d <= 1'b0 ; // retry must not be retried, since there is not a first data
|
retried_d = 1'b0 ; // retry must not be retried, since there is not a first data
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
default :
|
default :
|
begin
|
begin
|
addr_count <= 1'b0 ;
|
addr_count = 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_count_enable = 1'b0 ;
|
read_rty_cnt_exp_out <= 1'b0 ;
|
read_rty_cnt_exp_out = 1'b0 ;
|
wait_for_wb_response <= 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
|
wait_for_wb_response = 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
|
if((rty_counter_almost_max_value)&&(set_retry)) // when no WB response and RTY CNT reached maximum allowed value
|
if((rty_counter_almost_max_value)&&(set_retry)) // when no WB response and RTY CNT reached maximum allowed value
|
begin
|
begin
|
retried_d <= 1'b1 ;
|
retried_d = 1'b1 ;
|
n_state <= S_TURN_ARROUND ; // go here to stop read request
|
n_state = S_TURN_ARROUND ; // go here to stop read request
|
pcir_fifo_wenable <= 1'b1 ;
|
pcir_fifo_wenable = 1'b1 ;
|
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`LAST_CTRL_BIT] = 1'b0 ;
|
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b1 ; // FIFO must indicate the DATA with ERROR
|
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b1 ; // FIFO must indicate the DATA with ERROR
|
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`UNUSED_CTRL_BIT] = 1'b0 ;
|
pcir_fifo_control[`ADDR_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ;
|
last_data_transferred <= 1'b1 ;
|
last_data_transferred = 1'b1 ;
|
wb_read_done <= 1'b1 ;
|
wb_read_done = 1'b1 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
retried_d <= 1'b0 ;
|
retried_d = 1'b0 ;
|
n_state <= S_READ ; // stay in S_READ state to wait WB to response
|
n_state = S_READ ; // stay in S_READ state to wait WB to response
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable = 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control = 4'h0 ;
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done = 1'b0 ;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
wb_stb_o <= 1'b1 ;
|
wb_stb_o = 1'b1 ;
|
wb_we_o <= 1'b0 ;
|
wb_we_o = 1'b0 ;
|
wb_cyc_o <= 1'b1 ;
|
wb_cyc_o = 1'b1 ;
|
end
|
end
|
S_READ_RTY: // Wait for PCI Target to remove read request, when retry counter reaches maximum value!
|
S_READ_RTY: // Wait for PCI Target to remove read request, when retry counter reaches maximum value!
|
begin
|
begin
|
// Default values for signals not used in this state
|
// Default values for signals not used in this state
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable = 1'b0 ;
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable = 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control = 4'h0 ;
|
addr_into_cnt <= 1'b0 ;
|
addr_into_cnt = 1'b0 ;
|
read_count_load <= 1'b0 ;
|
read_count_load = 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_count_enable = 1'b0 ;
|
addr_count <= 1'b0 ;
|
addr_count = 1'b0 ;
|
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out = 1'b0 ;
|
error_source_out <= 1'b0 ;
|
error_source_out = 1'b0 ;
|
retried_d <= 1'b0 ;
|
retried_d = 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done = 1'b0 ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
write_rty_cnt_exp_out = 1'b0 ;
|
read_rty_cnt_exp_out <= 1'b0 ;
|
read_rty_cnt_exp_out = 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
// wait for PCI Target to remove read request
|
// wait for PCI Target to remove read request
|
if (pci_tar_read_request)
|
if (pci_tar_read_request)
|
begin
|
begin
|
n_state <= S_READ_RTY ; // stay in this state until read request is removed
|
n_state = S_READ_RTY ; // stay in this state until read request is removed
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
end
|
end
|
else // when read request is removed
|
else // when read request is removed
|
begin
|
begin
|
n_state <= S_IDLE ;
|
n_state = S_IDLE ;
|
last_data_transferred <= 1'b1 ; // when read request is removed, there is "last" data
|
last_data_transferred = 1'b1 ; // when read request is removed, there is "last" data
|
end
|
end
|
wb_stb_o <= 1'b0 ;
|
wb_stb_o = 1'b0 ;
|
wb_we_o <= 1'b0 ;
|
wb_we_o = 1'b0 ;
|
wb_cyc_o <= 1'b0 ;
|
wb_cyc_o = 1'b0 ;
|
end
|
end
|
S_TURN_ARROUND: // Turn arround cycle after writting to PCIR_FIFO (for correct data when reading from PCIW_FIFO)
|
S_TURN_ARROUND: // Turn arround cycle after writting to PCIR_FIFO (for correct data when reading from PCIW_FIFO)
|
begin
|
begin
|
// Default values for signals not used in this state
|
// Default values for signals not used in this state
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable = 1'b0 ;
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable = 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control = 4'h0 ;
|
addr_into_cnt <= 1'b0 ;
|
addr_into_cnt = 1'b0 ;
|
read_count_load <= 1'b0 ;
|
read_count_load = 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_count_enable = 1'b0 ;
|
addr_count <= 1'b0 ;
|
addr_count = 1'b0 ;
|
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out = 1'b0 ;
|
error_source_out <= 1'b0 ;
|
error_source_out = 1'b0 ;
|
retried_d <= 1'b0 ;
|
retried_d = 1'b0 ;
|
last_data_transferred <= 1'b1 ;
|
last_data_transferred = 1'b1 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done = 1'b0 ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
write_rty_cnt_exp_out = 1'b0 ;
|
read_rty_cnt_exp_out <= 1'b0 ;
|
read_rty_cnt_exp_out = 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
n_state <= S_IDLE ;
|
n_state = S_IDLE ;
|
wb_stb_o <= 1'b0 ;
|
wb_stb_o = 1'b0 ;
|
wb_we_o <= 1'b0 ;
|
wb_we_o = 1'b0 ;
|
wb_cyc_o <= 1'b0 ;
|
wb_cyc_o = 1'b0 ;
|
end
|
end
|
default :
|
default :
|
begin
|
begin
|
// Default values for signals not used in this state
|
// Default values for signals not used in this state
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable = 1'b0 ;
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable = 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control = 4'h0 ;
|
addr_into_cnt <= 1'b0 ;
|
addr_into_cnt = 1'b0 ;
|
read_count_load <= 1'b0 ;
|
read_count_load = 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_count_enable = 1'b0 ;
|
addr_count <= 1'b0 ;
|
addr_count = 1'b0 ;
|
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out = 1'b0 ;
|
error_source_out <= 1'b0 ;
|
error_source_out = 1'b0 ;
|
retried_d <= 1'b0 ;
|
retried_d = 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done = 1'b0 ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
write_rty_cnt_exp_out = 1'b0 ;
|
read_rty_cnt_exp_out <= 1'b0 ;
|
read_rty_cnt_exp_out = 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
n_state <= S_IDLE ;
|
n_state = S_IDLE ;
|
wb_stb_o <= 1'b0 ;
|
wb_stb_o = 1'b0 ;
|
wb_we_o <= 1'b0 ;
|
wb_we_o = 1'b0 ;
|
wb_cyc_o <= 1'b0 ;
|
wb_cyc_o = 1'b0 ;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// Signal for retry monitor in state machine when there is read and first (or single) data access
|
// Signal for retry monitor in state machine when there is read and first (or single) data access
|
| Line 1023... |
Line 1026... |
reg wb_cyc_reg ;
|
reg wb_cyc_reg ;
|
always@(posedge wb_clock_in or posedge reset_in)
|
always@(posedge wb_clock_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
no_sel_o_change_due_rty <= 1'b0;
|
no_sel_o_change_due_rty <= #`FF_DELAY 1'b0;
|
CYC_O <= 1'h0 ;
|
CYC_O <= #`FF_DELAY 1'h0 ;
|
STB_O <= 1'h0 ;
|
STB_O <= #`FF_DELAY 1'h0 ;
|
WE_O <= 1'h0 ;
|
WE_O <= #`FF_DELAY 1'h0 ;
|
CAB_O <= 1'h0 ;
|
CAB_O <= #`FF_DELAY 1'h0 ;
|
MDATA_O <= 32'h0 ;
|
MDATA_O <= #`FF_DELAY 32'h0 ;
|
SEL_O <= 4'h0 ;
|
SEL_O <= #`FF_DELAY 4'h0 ;
|
wb_cyc_reg <= 1'h0 ;
|
wb_cyc_reg <= #`FF_DELAY 1'h0 ;
|
wb_read_done_out <= 1'b0 ;
|
wb_read_done_out <= #`FF_DELAY 1'b0 ;
|
pcir_fifo_data_out <= 32'h0 ;
|
pcir_fifo_data_out <= #`FF_DELAY 32'h0 ;
|
pcir_fifo_wenable_out <= 1'b0 ;
|
pcir_fifo_wenable_out <= #`FF_DELAY 1'b0 ;
|
pcir_fifo_control_out <= 1'b0 ;
|
pcir_fifo_control_out <= #`FF_DELAY 1'b0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (w_attempt)
|
if (w_attempt)
|
if (ACK_I || ERR_I || last_data_transferred)
|
if (ACK_I || ERR_I || last_data_transferred)
|
no_sel_o_change_due_rty <= 1'b0;
|
no_sel_o_change_due_rty <= #`FF_DELAY 1'b0;
|
else if (retry)
|
else if (retry)
|
no_sel_o_change_due_rty <= 1'b1;
|
no_sel_o_change_due_rty <= #`FF_DELAY 1'b1;
|
if (wb_cyc_o)
|
if (wb_cyc_o)
|
begin // retry = RTY_I || set_retry
|
begin // retry = RTY_I || set_retry
|
CYC_O <= ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) ;
|
CYC_O <= #`FF_DELAY ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) ;
|
CAB_O <= ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) && burst_transfer ;
|
CAB_O <= #`FF_DELAY ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) && burst_transfer ;
|
STB_O <= ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) ;
|
STB_O <= #`FF_DELAY ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) ;
|
end
|
end
|
WE_O <= wb_we_o ;
|
WE_O <= #`FF_DELAY wb_we_o ;
|
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
|
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
|
MDATA_O <= pciw_fifo_addr_data_in ;
|
MDATA_O <= #`FF_DELAY pciw_fifo_addr_data_in ;
|
if (w_attempt)
|
if (w_attempt)
|
begin
|
begin
|
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
|
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
|
SEL_O <= ~pciw_fifo_cbe_in ;
|
SEL_O <= #`FF_DELAY ~pciw_fifo_cbe_in ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if ((wb_cyc_o && ~wb_cyc_reg) || ACK_I)
|
if ((wb_cyc_o && ~wb_cyc_reg) || ACK_I)
|
SEL_O <= wb_sel_o ;
|
SEL_O <= #`FF_DELAY wb_sel_o ;
|
end
|
end
|
wb_cyc_reg <= wb_cyc_o ;
|
wb_cyc_reg <= #`FF_DELAY wb_cyc_o ;
|
wb_read_done_out <= wb_read_done ;
|
wb_read_done_out <= #`FF_DELAY wb_read_done ;
|
pcir_fifo_data_out <= MDATA_I ;
|
pcir_fifo_data_out <= #`FF_DELAY MDATA_I ;
|
pcir_fifo_wenable_out <= pcir_fifo_wenable ;
|
pcir_fifo_wenable_out <= #`FF_DELAY pcir_fifo_wenable ;
|
pcir_fifo_control_out <= pcir_fifo_control ;
|
pcir_fifo_control_out <= #`FF_DELAY pcir_fifo_control ;
|
end
|
end
|
end
|
end
|
always@(pciw_fifo_renable or last_data_from_pciw_fifo_reg or wb_cyc_o or wb_cyc_reg or wb_we_o or retried_write or
|
always@(pciw_fifo_renable or last_data_from_pciw_fifo_reg or wb_cyc_o or wb_cyc_reg or wb_we_o or retried_write or
|
pciw_fifo_control_in or pciw_fifo_empty_in)
|
pciw_fifo_control_in or pciw_fifo_empty_in)
|
begin
|
begin
|
pciw_fifo_renable_out <= (pciw_fifo_renable && ~wb_cyc_o) ||
|
pciw_fifo_renable_out <= #`FF_DELAY (pciw_fifo_renable && ~wb_cyc_o) ||
|
(pciw_fifo_renable && ~last_data_from_pciw_fifo_reg) ||
|
(pciw_fifo_renable && ~last_data_from_pciw_fifo_reg) ||
|
(wb_cyc_o && ~wb_cyc_reg && wb_we_o && !retried_write) ;
|
(wb_cyc_o && ~wb_cyc_reg && wb_we_o && !retried_write) ;
|
last_data_from_pciw_fifo_reg <= pciw_fifo_control_in[`ADDR_CTRL_BIT] || pciw_fifo_empty_in ;
|
last_data_from_pciw_fifo_reg <= #`FF_DELAY pciw_fifo_control_in[`ADDR_CTRL_BIT] || pciw_fifo_empty_in ;
|
end
|
end
|
`else
|
`else
|
always@(wb_cyc_o or wb_stb_o or wb_we_o or burst_transfer or pciw_fifo_addr_data_in or wb_sel_o or
|
always@(wb_cyc_o or wb_stb_o or wb_we_o or burst_transfer or pciw_fifo_addr_data_in or wb_sel_o or
|
wb_read_done or MDATA_I or pcir_fifo_wenable or pcir_fifo_control)
|
wb_read_done or MDATA_I or pcir_fifo_wenable or pcir_fifo_control)
|
begin
|
begin
|
CYC_O <= wb_cyc_o ;
|
CYC_O = wb_cyc_o ;
|
STB_O <= wb_stb_o ;
|
STB_O = wb_stb_o ;
|
WE_O <= wb_we_o ;
|
WE_O = wb_we_o ;
|
CAB_O <= wb_cyc_o & burst_transfer ;
|
CAB_O = wb_cyc_o & burst_transfer ;
|
MDATA_O <= pciw_fifo_addr_data_in ;
|
MDATA_O = pciw_fifo_addr_data_in ;
|
SEL_O <= wb_sel_o ;
|
SEL_O = wb_sel_o ;
|
wb_read_done_out <= wb_read_done ;
|
wb_read_done_out = wb_read_done ;
|
pcir_fifo_data_out <= MDATA_I ;
|
pcir_fifo_data_out = MDATA_I ;
|
pcir_fifo_wenable_out <= pcir_fifo_wenable ;
|
pcir_fifo_wenable_out = pcir_fifo_wenable ;
|
pcir_fifo_control_out <= pcir_fifo_control ;
|
pcir_fifo_control_out = pcir_fifo_control ;
|
end
|
end
|
always@(pciw_fifo_renable or last_data_from_pciw_fifo)
|
always@(pciw_fifo_renable or last_data_from_pciw_fifo)
|
begin
|
begin
|
pciw_fifo_renable_out <= pciw_fifo_renable ;
|
pciw_fifo_renable_out = pciw_fifo_renable ;
|
last_data_from_pciw_fifo_reg <= last_data_from_pciw_fifo ;
|
last_data_from_pciw_fifo_reg = last_data_from_pciw_fifo ;
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
endmodule
|
endmodule
|
