URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_master.v] - Diff between revs 65 and 72

Rev 65	Rev 72
Line 40...	Line 40...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2002/10/11 14:15:29 mihad`
	`// Cleaned up non-blocking assignments in combinatinal logic statements`
	`//`
`// Revision 1.5 2002/03/05 11:53:47 mihad`	`// Revision 1.5 2002/03/05 11:53:47 mihad`
`// Added some testcases, removed un-needed fifo signals`	`// Added some testcases, removed un-needed fifo signals`
`//`	`//`
`// Revision 1.4 2002/02/19 16:32:37 mihad`	`// Revision 1.4 2002/02/19 16:32:37 mihad`
`// Modified testbench and fixed some bugs`	`// Modified testbench and fixed some bugs`
Line 534...	Line 537...
`begin`	`begin`
`first_data_is_burst = 1'b0 ;`	`first_data_is_burst = 1'b0 ;`
`end`	`end`
`end`	`end`
`else`	`else`
first_data_is_burst = pciw_fifo_control_in[`BURST_BIT] && ~pciw_fifo_empty_in ;	first_data_is_burst = pciw_fifo_control_in[`BURST_BIT] && ~pciw_fifo_empty_in && ~pciw_fifo_control_in[`LAST_CTRL_BIT];
`end`	`end`

`// FF for seting and reseting burst_transfer signal`	`// FF for seting and reseting burst_transfer signal`
`always@(posedge wb_clock_in or posedge reset_in)`	`always@(posedge wb_clock_in or posedge reset_in)`
`begin`	`begin`