| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
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// CVS Revision History
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//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2001/10/05 08:14:30 mihad
|
|
// Updated all files with inclusion of timescale file for simulation purposes.
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|
//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
|
// New project directory structure
|
//
|
//
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//
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//
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|
|
`include "bus_commands.v"
|
`include "bus_commands.v"
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`include "constants.v"
|
`include "pci_constants.v"
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|
|
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
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|
// synopsys translate_on
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|
|
module WB_SLAVE( wb_clock_in,
|
module WB_SLAVE( wb_clock_in,
|
reset_in,
|
reset_in,
|
wb_hit_in,
|
wb_hit_in,
|
wb_conf_hit_in,
|
wb_conf_hit_in,
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| Line 92... |
Line 98... |
wbr_fifo_control_in,
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wbr_fifo_control_in,
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wbr_fifo_flush_out,
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wbr_fifo_flush_out,
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wbr_fifo_empty_in,
|
wbr_fifo_empty_in,
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pciw_fifo_empty_in,
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pciw_fifo_empty_in,
|
wbs_lock_in,
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wbs_lock_in,
|
|
cache_line_size_not_zero,
|
|
sample_address_out,
|
CYC_I,
|
CYC_I,
|
STB_I,
|
STB_I,
|
WE_I,
|
WE_I,
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SEL_I,
|
SEL_I,
|
SDATA_I,
|
SDATA_I,
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| Line 226... |
Line 234... |
|
|
// used for transaction ordering requirements - WISHBONE read cannot complete until writes from PCI are completed
|
// used for transaction ordering requirements - WISHBONE read cannot complete until writes from PCI are completed
|
input pciw_fifo_empty_in ; // empty status indicator from PCIW_FIFO
|
input pciw_fifo_empty_in ; // empty status indicator from PCIW_FIFO
|
|
|
/*----------------------------------------------------------------------------------------------------------------------
|
/*----------------------------------------------------------------------------------------------------------------------
|
wbs_lock_in - internal signal - when error reporting is enabled and PCI master detects an error while completing
|
wbs_lock_in: internal signal that locks out all accesses, except delayed completions or configuration accesses.
|
posted write on PCI, then WISHBONE slave unit doesn't accept any new requests or posted writes. Delayed completions
|
( when master operation is disabled via master enable bit in configuration spacei )
|
are allowed to complete on WISHBONE if all other requirements are satisfied also.
|
|
---------------------------------------------------------------------------------------------------------------------*/
|
---------------------------------------------------------------------------------------------------------------------*/
|
input wbs_lock_in ;
|
input wbs_lock_in ;
|
|
|
|
// cache line size register must hold appropriate value to enable read bursts and special commands on PCI bus!
|
|
input cache_line_size_not_zero ;
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|
|
|
// state machine signals to wb_addr_mux when to sample wb address input
|
|
output sample_address_out ;
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|
reg sample_address_out ;
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|
|
/*----------------------------------------------------------------------------------------------------------------------
|
/*----------------------------------------------------------------------------------------------------------------------
|
WISHBONE bus interface signals - can be connected directly to WISHBONE bus
|
WISHBONE bus interface signals - can be connected directly to WISHBONE bus
|
---------------------------------------------------------------------------------------------------------------------*/
|
---------------------------------------------------------------------------------------------------------------------*/
|
input CYC_I ; // cycle indicator
|
input CYC_I ; // cycle indicator
|
input STB_I ; // strobe input - input data is valid when strobe and cycle indicator are high
|
input STB_I ; // strobe input - input data is valid when strobe and cycle indicator are high
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| Line 246... |
Line 260... |
output ACK_O ; // Acknowledge output - qualifies valid data on data output bus or received data on data input bus
|
output ACK_O ; // Acknowledge output - qualifies valid data on data output bus or received data on data input bus
|
output RTY_O ; // retry output - signals to WISHBONE master that cycle should be terminated and retried later
|
output RTY_O ; // retry output - signals to WISHBONE master that cycle should be terminated and retried later
|
output ERR_O ; // Signals to WISHBONE master that access resulted in an error
|
output ERR_O ; // Signals to WISHBONE master that access resulted in an error
|
input CAB_I ; // consecutive address burst input - indicates that master will do a serial address transfer in current cycle
|
input CAB_I ; // consecutive address burst input - indicates that master will do a serial address transfer in current cycle
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|
|
|
`ifdef REGISTER_WBS_OUTPUTS
|
|
reg [31:0] SDATA_O ;
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|
reg ACK_O ;
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|
reg RTY_O ;
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|
reg ERR_O ;
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|
|
|
reg [3:0] del_bc_out ; // delayed transaction bus command output
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|
reg del_req_out ; // output for issuing delayed transaction requests
|
|
reg del_done_out ; // output indicating current delayed completion finished on WISHBONE bus
|
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reg del_burst_out ; // delayed burst transaction indicator
|
|
reg del_in_progress_out ; // delayed in progress indicator - since delayed transaction can be a burst transaction, progress indicator must be used for proper operation
|
|
reg del_write_out ; // write enable for delayed transaction - used for indicating that transaction is a write
|
|
|
|
`ifdef HOST
|
|
reg wb_conf_wenable_out ;
|
|
reg [31:0] wb_conf_data_out ; // configuration data output for configuration space
|
|
`endif
|
|
|
|
reg [3:0] wb_conf_be_out ; // byte enable outputs for configuration space
|
|
reg [31:0] wb_data_out ;
|
|
|
|
reg [3:0] wb_cbe_out ;
|
|
|
|
reg wbw_fifo_wenable_out ; // write enable for WBW_FIFO output
|
|
reg [3:0] wbw_fifo_control_out ; // control bus output for WBW_FIFO
|
|
|
|
reg wbr_fifo_renable_out ; // WBR_FIFO read enable output
|
|
`endif
|
|
|
reg [(`FSM_BITS - 1):0] c_state ; //current state register
|
reg [(`FSM_BITS - 1):0] c_state ; //current state register
|
// synopsys state_vector c_state
|
|
|
|
reg [(`FSM_BITS - 1):0] n_state ; //next state input to current state register
|
reg [(`FSM_BITS - 1):0] n_state ; //next state input to current state register
|
|
|
// lock register - lock signal can cross clock domains, so here is register for it
|
|
reg lock ;
|
|
always@(posedge reset_in or posedge wb_clock_in)
|
|
begin
|
|
if (reset_in)
|
|
lock <= #`FF_DELAY 1'b0 ;
|
|
else
|
|
lock <= #`FF_DELAY wbs_lock_in ;
|
|
end
|
|
|
|
// state machine register control
|
// state machine register control
|
always@(posedge wb_clock_in or posedge reset_in)
|
always@(posedge wb_clock_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
c_state <= #`FF_DELAY S_IDLE ;
|
c_state <= #`FF_DELAY S_IDLE ;
|
else
|
else
|
c_state <= #`FF_DELAY n_state ;
|
c_state <= #`FF_DELAY n_state ;
|
end
|
end
|
|
|
|
|
// write operation indicator for delayed transaction requests
|
|
assign del_write_out = WE_I ;
|
|
|
|
// variable for bus command multiplexer logic output for delayed requests
|
// variable for bus command multiplexer logic output for delayed requests
|
reg [3:0] del_bc ;
|
reg [3:0] del_bc ;
|
|
|
//register for intermediate data and select storage
|
//register for intermediate data and select storage
|
reg [35:0] d_incoming ;
|
reg [35:0] d_incoming ;
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| Line 299... |
Line 328... |
- WBW_FIFO musn't be almost full nor full for image writes to be allowed - Every transaction takes at least two locations in the FIFO
|
- WBW_FIFO musn't be almost full nor full for image writes to be allowed - Every transaction takes at least two locations in the FIFO
|
- delayed read from from WISHBONE to PCI request musn't be present
|
- delayed read from from WISHBONE to PCI request musn't be present
|
- delayed read from PCI to WISHBONE completion musn't be present
|
- delayed read from PCI to WISHBONE completion musn't be present
|
- lock input musn't be set - it can be set because of error reporting or because PCI master state machine is disabled
|
- lock input musn't be set - it can be set because of error reporting or because PCI master state machine is disabled
|
===================================================================================================================================================================================*/
|
===================================================================================================================================================================================*/
|
wire wimg_wallow = ~|{ wbw_fifo_almost_full_in , wbw_fifo_full_in, wb_del_req_pending_in, pci_drcomp_pending_in, lock } ;
|
wire wimg_wallow = ~|{ wbw_fifo_almost_full_in , wbw_fifo_full_in, wb_del_req_pending_in, pci_drcomp_pending_in, wbs_lock_in } ;
|
reg decode_en ;
|
|
reg img_wallow ;
|
reg img_wallow ;
|
always@(posedge reset_in or posedge wb_clock_in)
|
|
begin
|
|
if (reset_in)
|
|
img_wallow <= #`FF_DELAY 1'b0 ;
|
|
else
|
|
if (decode_en)
|
|
img_wallow <= #`FF_DELAY wimg_wallow ;
|
|
end
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|
|
|
|
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/*===================================================================================================================================================================================
|
/*===================================================================================================================================================================================
|
WISHBONE slave can request an image read accesses when all of following are true:
|
WISHBONE slave can request an image read accesses when all of following are true:
|
- delayed completion is not present
|
- delayed completion is not present
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- delayed request is not present
|
- delayed request is not present
|
- operation is not locked because of error reporting mechanism or because PCI master is disabled
|
- operation is not locked because of error reporting mechanism or because PCI master is disabled
|
===================================================================================================================================================================================*/
|
===================================================================================================================================================================================*/
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wire wdo_del_request = ~|{ wb_del_req_pending_in, wb_del_comp_pending_in, lock } ;
|
wire wdo_del_request = ~|{ wb_del_req_pending_in, wb_del_comp_pending_in, wbs_lock_in } ;
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reg do_del_request ;
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reg do_del_request ;
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always@(posedge reset_in or posedge wb_clock_in)
|
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begin
|
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if (reset_in)
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do_del_request <= #`FF_DELAY 1'b0 ;
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else
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if (decode_en)
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do_del_request <= #`FF_DELAY wdo_del_request ;
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end
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/*===================================================================================================================================================================================
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/*===================================================================================================================================================================================
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WISHBONE slave can complete an image read accesses when all of following are true:
|
WISHBONE slave can complete an image read accesses when all of following are true:
|
- delayed read completion is present
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- delayed read completion is present
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- delayed read completion is the same as current read access ( dread_completion_hit is 1 )
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- delayed read completion is the same as current read access ( dread_completion_hit is 1 )
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- PCI Write FIFO is empty - no posted write is waiting to be finished in PCIW_FIFO
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- PCI Write FIFO is empty - no posted write is waiting to be finished in PCIW_FIFO
|
- WBR_FIFO empty status is active
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- WBR_FIFO empty status is not active
|
===================================================================================================================================================================================*/
|
===================================================================================================================================================================================*/
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wire del_bc_hit = ( del_bc == del_bc_in ) ;
|
|
|
|
wire wdel_addr_hit = ( wb_del_addr_in == wb_addr_in ) && ( SEL_I == wb_del_be_in ) ;
|
wire wdel_addr_hit = ( wb_del_addr_in == wb_addr_in ) && ( SEL_I == wb_del_be_in ) ;
|
reg del_addr_hit ;
|
reg del_addr_hit ;
|
always@(posedge reset_in or posedge wb_clock_in)
|
|
begin
|
|
if (reset_in)
|
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del_addr_hit <= #`FF_DELAY 1'b0 ;
|
|
else
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if ( decode_en )
|
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del_addr_hit <= #`FF_DELAY wdel_addr_hit ;
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|
end
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wire wdel_completion_allow = wb_del_comp_pending_in && ((~del_write_in && ~WE_I && pciw_fifo_empty_in && ~wbr_fifo_empty_in) || (del_write_in && WE_I)) ;
|
wire wdel_completion_allow = wb_del_comp_pending_in && ((~del_write_in && ~WE_I && pciw_fifo_empty_in && ~wbr_fifo_empty_in) || (del_write_in && WE_I)) ;
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|
|
reg del_completion_allow ;
|
reg del_completion_allow ;
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/*----------------------------------------------------------------------------------------------------------------------
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|
img_hit - state of wb_hit_in bus when when state machine signals decode is over
|
|
---------------------------------------------------------------------------------------------------------------------*/
|
|
reg [4:0] img_hit ;
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|
wire wb_hit = |( img_hit ) ;
|
|
|
|
/*----------------------------------------------------------------------------------------------------------------------
|
|
Control logic for image control signals
|
|
pref_en - prefetch enable of currently selected image
|
|
mrl_en - Memory read line enable of currently selected image
|
|
map - Address space mapping for currently selected image
|
|
---------------------------------------------------------------------------------------------------------------------*/
|
|
reg pref_en, mrl_en, map ;
|
|
wire wpref_en = |(wb_pref_en_in & wb_hit_in) ;
|
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wire wmrl_en = |(wb_mrl_en_in & wb_hit_in) ;
|
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wire wmap = |(wb_map_in & wb_hit_in) ;
|
|
|
|
// state machine controls when results from decoders, comparison etc. are sampled into registers to decode an access
|
|
reg decode_en ;
|
|
|
|
reg wb_conf_hit ;
|
always@(posedge reset_in or posedge wb_clock_in)
|
always@(posedge reset_in or posedge wb_clock_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
|
begin
|
|
img_wallow <= #`FF_DELAY 1'b0 ;
|
|
wb_conf_hit <= #`FF_DELAY 1'b0 ;
|
|
do_del_request <= #`FF_DELAY 1'b0 ;
|
|
del_addr_hit <= #`FF_DELAY 1'b0 ;
|
del_completion_allow <= #`FF_DELAY 1'b0 ;
|
del_completion_allow <= #`FF_DELAY 1'b0 ;
|
|
img_hit <= #`FF_DELAY 5'h00 ;
|
|
pref_en <= #`FF_DELAY 1'b0 ;
|
|
mrl_en <= #`FF_DELAY 1'b0 ;
|
|
map <= #`FF_DELAY 1'b0 ;
|
|
end
|
else
|
else
|
if ( decode_en )
|
if ( decode_en )
|
|
begin
|
|
img_wallow <= #`FF_DELAY wimg_wallow ;
|
|
wb_conf_hit <= #`FF_DELAY wb_conf_hit_in ;
|
|
do_del_request <= #`FF_DELAY wdo_del_request ;
|
|
del_addr_hit <= #`FF_DELAY wdel_addr_hit ;
|
del_completion_allow <= #`FF_DELAY wdel_completion_allow ;
|
del_completion_allow <= #`FF_DELAY wdel_completion_allow ;
|
|
img_hit <= #`FF_DELAY wb_hit_in ;
|
|
pref_en <= #`FF_DELAY wpref_en && cache_line_size_not_zero ;
|
|
mrl_en <= #`FF_DELAY wmrl_en && cache_line_size_not_zero ;
|
|
map <= #`FF_DELAY wmap ;
|
|
end
|
end
|
end
|
|
|
wire do_dread_completion = del_completion_allow && del_bc_hit && del_addr_hit ;
|
wire del_burst = CAB_I && (pref_en || mrl_en) && ~WE_I && cache_line_size_not_zero ; // delayed burst indicator - only when WB master attempts CAB transfer and cache line size register is set appropriately and
|
|
// either prefetch enable or memory read line enable of corresponding image are set -
|
|
// applies for reads only - delayed write cannot be a burst
|
|
wire do_dread_completion = del_completion_allow && del_addr_hit ;
|
|
|
// address allignement indicator
|
// address allignement indicator
|
wire alligned_address = ~|(wb_addr_in[1:0]) ;
|
wire alligned_address = ~|(wb_addr_in[1:0]) ;
|
|
|
`ifdef GUEST
|
`ifdef GUEST
|
| Line 384... |
Line 426... |
|
|
// configuration cycle data register hit
|
// configuration cycle data register hit
|
wire ccyc_hit = 1'b0 ;
|
wire ccyc_hit = 1'b0 ;
|
wire iack_hit = 1'b0 ;
|
wire iack_hit = 1'b0 ;
|
|
|
|
wire wccyc_hit = 1'b0 ;
|
|
wire wiack_hit = 1'b0 ;
|
|
|
`else
|
`else
|
`ifdef HOST
|
`ifdef HOST
|
// only host implementation has access for generating interrupt acknowledge and configuration cycles
|
// only host implementation has access for generating interrupt acknowledge and configuration cycles
|
// configuration cycle data register hit
|
// configuration cycle data register hit
|
wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR}) && alligned_address ;
|
reg current_delayed_is_ccyc ;
|
reg ccyc_hit ;
|
reg current_delayed_is_iack ;
|
always@(posedge reset_in or posedge wb_clock_in)
|
|
begin
|
|
if (reset_in)
|
|
ccyc_hit <= #`FF_DELAY 1'b0 ;
|
|
else
|
|
if (decode_en)
|
|
ccyc_hit <= #`FF_DELAY wccyc_hit ;
|
|
end
|
|
|
|
|
wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR}) && alligned_address ;
|
wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR}) && alligned_address ;
|
wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR}) && alligned_address ;
|
reg iack_hit ;
|
reg iack_hit ;
|
|
reg ccyc_hit ;
|
always@(posedge reset_in or posedge wb_clock_in)
|
always@(posedge reset_in or posedge wb_clock_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
|
begin
|
|
ccyc_hit <= #`FF_DELAY 1'b0 ;
|
iack_hit <= #`FF_DELAY 1'b0 ;
|
iack_hit <= #`FF_DELAY 1'b0 ;
|
|
end
|
else
|
else
|
if (decode_en)
|
if (decode_en)
|
|
begin
|
|
ccyc_hit <= #`FF_DELAY wccyc_hit ;
|
iack_hit <= #`FF_DELAY wiack_hit ;
|
iack_hit <= #`FF_DELAY wiack_hit ;
|
end
|
end
|
|
end
|
|
|
// wires indicating allowance for configuration cycle generation requests
|
// wires indicating allowance for configuration cycle generation requests
|
wire do_ccyc_req = do_del_request && ccyc_hit;
|
wire do_ccyc_req = do_del_request && ccyc_hit;
|
wire do_ccyc_comp = del_completion_allow && del_bc_hit && ccyc_hit;
|
wire do_ccyc_comp = del_completion_allow && ccyc_hit && current_delayed_is_ccyc ; // && del_bc_hit
|
|
|
// wires indicating allowance for interrupt acknowledge cycle generation requests
|
// wires indicating allowance for interrupt acknowledge cycle generation requests
|
wire do_iack_req = do_del_request && iack_hit ;
|
wire do_iack_req = do_del_request && iack_hit ;
|
wire do_iack_comp = del_completion_allow && del_bc_hit && ccyc_hit;
|
wire do_iack_comp = del_completion_allow && iack_hit && current_delayed_is_iack ; // && del_bc_hit
|
|
|
// variables for configuration access control signals
|
// variables for configuration access control signals
|
reg conf_wenable ;
|
reg conf_wenable ;
|
assign wb_conf_wenable_out = conf_wenable ;
|
|
|
// following flip-flops remember whether current delayed transaction is interrupt acknowledge or configuration cycle transaction
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
begin
|
|
current_delayed_is_ccyc <= #`FF_DELAY 1'b0 ;
|
|
current_delayed_is_iack <= #`FF_DELAY 1'b0 ;
|
|
end
|
|
else
|
|
if ( del_done_out )
|
|
begin
|
|
current_delayed_is_ccyc <= #`FF_DELAY 1'b0 ;
|
|
current_delayed_is_iack <= #`FF_DELAY 1'b0 ;
|
|
end
|
|
else
|
|
if ( del_req_out && wb_conf_hit )
|
|
begin
|
|
current_delayed_is_ccyc <= #`FF_DELAY do_ccyc_req ;
|
|
current_delayed_is_iack <= #`FF_DELAY do_iack_req ;
|
|
end
|
|
end
|
|
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
// configuration read enable - supplied for host and guest bridges
|
// configuration read enable - supplied for host and guest bridges
|
reg conf_renable ;
|
reg conf_renable ;
|
assign wb_conf_renable_out = conf_renable ;
|
assign wb_conf_renable_out = conf_renable ;
|
|
|
// wire for write attempt - 1 when external WB master is attempting a write
|
|
wire wattempt = ( CYC_I && STB_I && WE_I ) ; // write is qualified when cycle, strobe and write enable inputs are all high
|
|
|
|
// wire for read attempt - 1 when external WB master is attempting a read
|
|
wire rattempt = ( CYC_I && STB_I && ~WE_I ) ; // read is qualified when cycle and strobe are high and write enable is low
|
|
|
|
// burst access indicator
|
// burst access indicator
|
wire burst_transfer = CYC_I && CAB_I ;
|
wire burst_transfer = CYC_I && CAB_I ;
|
|
|
// SEL_I error indicator for IO and configuration accesses - select lines must be alligned with address
|
// SEL_I error indicator for IO accesses - select lines must be alligned with address
|
reg sel_error ;
|
reg sel_error ;
|
always@(wb_addr_in or SEL_I)
|
always@(wb_addr_in or SEL_I)
|
begin
|
begin
|
case (wb_addr_in[1:0])
|
case (wb_addr_in[1:0])
|
2'b00: sel_error = ~SEL_I[0] ; // select 0 must be 1, all others are don't cares.
|
2'b00: sel_error = ~SEL_I[0] ; // select 0 must be 1, all others are don't cares.
|
| Line 453... |
Line 512... |
endcase
|
endcase
|
end
|
end
|
|
|
// WBW_FIFO control output
|
// WBW_FIFO control output
|
reg [3:0] wbw_fifo_control ;
|
reg [3:0] wbw_fifo_control ;
|
assign wbw_fifo_control_out = wbw_fifo_control ; //control bus output for WBW_FIFO
|
|
|
|
// WBW_FIFO wenable output assignment
|
// WBW_FIFO wenable output assignment
|
reg wbw_fifo_wenable ;
|
reg wbw_fifo_wenable ;
|
assign wbw_fifo_wenable_out = wbw_fifo_wenable ; //write enable for WBW_FIFO
|
|
|
|
// WBR_FIFO control outputs
|
// WBR_FIFO control outputs
|
reg wbr_fifo_flush, wbr_fifo_renable ; // flush and read enable outputs
|
reg wbr_fifo_flush, wbr_fifo_renable ; // flush and read enable outputs
|
assign wbr_fifo_renable_out = wbr_fifo_renable ; //read enable for wbr_fifo
|
|
|
|
reg wbr_fifo_flush_out ;
|
// flush signal for WBR_FIFO must be registered, since it asinchronously resets some status registers
|
|
wire wbr_fifo_flush_reg ;
|
always@(posedge reset_in or posedge wb_clock_in)
|
async_reset_flop async_reset_as_wbr_flush
|
begin
|
(
|
if ( reset_in )
|
.data_in (wbr_fifo_flush),
|
wbr_fifo_flush_out <= #`FF_DELAY 1'b0 ;
|
.clk_in (wb_clock_in),
|
else
|
.async_reset_data_out (wbr_fifo_flush_reg),
|
wbr_fifo_flush_out <= #`FF_DELAY wbr_fifo_flush ;
|
.reset_in (reset_in)
|
end
|
) ;
|
|
assign wbr_fifo_flush_out = wbr_fifo_flush_reg ;
|
|
|
// delayed transaction request control signals
|
// delayed transaction request control signals
|
reg del_req, del_done ;
|
reg del_req, del_done ;
|
assign del_req_out = del_req ; // read request
|
|
assign del_done_out = del_done ; // read done
|
|
|
|
// WISHBONE handshaking control outputs
|
// WISHBONE handshaking control outputs
|
reg ack, rty, err ;
|
reg ack, rty, err ;
|
assign ACK_O = ack ;
|
|
assign RTY_O = rty ;
|
|
assign ERR_O = err ;
|
|
|
|
/*----------------------------------------------------------------------------------------------------------------------
|
|
Control logic for image hits
|
|
img_hit - state of wb_hit_in bus when first data is acknowledged
|
|
---------------------------------------------------------------------------------------------------------------------*/
|
|
reg [4:0] img_hit ;
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if (reset_in)
|
|
img_hit <= #`FF_DELAY 5'h00 ;
|
|
else
|
|
if (decode_en)
|
|
img_hit <= #`FF_DELAY wb_hit_in ;
|
|
end
|
|
|
|
wire wb_hit = |( img_hit ) ;
|
`ifdef REGISTER_WBS_OUTPUTS
|
|
// wire for write attempt - 1 when external WB master is attempting a write
|
/*----------------------------------------------------------------------------------------------------------------------
|
// wire for read attempt - 1 when external master is attempting a read
|
Control logic for image control signals
|
wire wattempt = ( CYC_I && STB_I && WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ;
|
pref_en - prefetch enable of currently selected image
|
wire rattempt = ( CYC_I && STB_I && ~WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ;
|
mrl_en - Memory read line enable of currently selected image
|
|
map - Address space mapping for currently selected image
|
|
---------------------------------------------------------------------------------------------------------------------*/
|
|
reg pref_en, mrl_en, map ;
|
|
|
|
wire wpref_en = |(wb_pref_en_in & wb_hit_in) ;
|
|
wire wmrl_en = |(wb_pref_en_in & wb_hit_in) ;
|
|
wire wmap = |(wb_map_in & wb_hit_in) ;
|
|
|
|
always@(posedge reset_in or posedge wb_clock_in)
|
|
begin
|
|
if (reset_in)
|
|
begin
|
|
pref_en <= #`FF_DELAY 1'b0 ;
|
|
mrl_en <= #`FF_DELAY 1'b0 ;
|
|
map <= #`FF_DELAY 1'b0 ;
|
|
end
|
|
else
|
|
if ( decode_en )
|
|
begin
|
|
pref_en <= #`FF_DELAY wpref_en ;
|
|
mrl_en <= #`FF_DELAY wmrl_en ;
|
|
map <= #`FF_DELAY wmap ;
|
|
end
|
|
end
|
|
|
|
assign del_burst_out = CAB_I && pref_en && ~WE_I; // delayed burst indicator - only when WB master attempts CAB transfer and prefetch enable of corresponding image is set -
|
`ifdef WB_DECODE_FAST
|
// applies for reads only - delayed write cannot be a burst
|
`undef WB_DECODE_FAST
|
|
`define WB_DECODE_MEDIUM
|
|
`endif
|
|
|
reg wb_conf_hit ;
|
`else
|
always@(posedge reset_in or posedge wb_clock_in)
|
// wire for write attempt - 1 when external WB master is attempting a write
|
begin
|
// wire for read attempt - 1 when external master is attempting a read
|
if (reset_in)
|
wire wattempt = ( CYC_I && STB_I && WE_I ) ; // write is qualified when cycle, strobe and write enable inputs are all high
|
wb_conf_hit <= #`FF_DELAY 1'b0 ;
|
wire rattempt = ( CYC_I && STB_I && ~WE_I ) ; // read is qualified when cycle and strobe are high and write enable is low
|
else
|
|
if (decode_en)
|
|
wb_conf_hit <= #`FF_DELAY wb_conf_hit_in ;
|
|
end
|
|
|
|
|
`endif
|
/*----------------------------------------------------------------------------------------------------------------------
|
/*----------------------------------------------------------------------------------------------------------------------
|
Delayed transaction bus command generation
|
Delayed transaction bus command generation
|
Bus command for delayed reads depends on image's address space mapping and control bits and
|
Bus command for delayed reads depends on image's address space mapping and control bits and
|
whether or not these are interrupt acknowledge requests or configuration cycle requests
|
whether or not these are interrupt acknowledge requests or configuration cycle requests
|
---------------------------------------------------------------------------------------------------------------------*/
|
---------------------------------------------------------------------------------------------------------------------*/
|
assign del_bc_out = del_bc ;
|
|
|
|
always@(map or mrl_en or ccyc_hit or WE_I or wb_conf_hit or CAB_I or pref_en)
|
always@(map or mrl_en or ccyc_hit or WE_I or wb_conf_hit or CAB_I or pref_en)
|
begin
|
begin
|
|
`ifdef HOST
|
|
// only host implementation supports configuration and interrupt acknowledge commands
|
if (wb_conf_hit)
|
if (wb_conf_hit)
|
begin
|
begin
|
case( {ccyc_hit, WE_I} )
|
case( {ccyc_hit, WE_I} )
|
2'b11: del_bc = `BC_CONF_WRITE ;
|
2'b11: del_bc = `BC_CONF_WRITE ;
|
2'b10: del_bc = `BC_CONF_READ ;
|
2'b10: del_bc = `BC_CONF_READ ;
|
2'b01: del_bc = `BC_IACK ;
|
2'b01: del_bc = `BC_RESERVED0 ; // invalid combination - interrupt acknowledge cycle must be a read
|
2'b00: del_bc = `BC_IACK ;
|
2'b00: del_bc = `BC_IACK ;
|
endcase
|
endcase
|
end
|
end
|
else
|
else
|
|
`endif
|
|
begin
|
|
if ( map )
|
|
begin
|
|
del_bc = `BC_IO_READ ;
|
|
end
|
|
else
|
begin
|
begin
|
case ( {map, CAB_I && mrl_en && pref_en} )
|
case ({(CAB_I && mrl_en), pref_en})
|
2'b11: del_bc = `BC_IO_READ ;
|
2'b00: del_bc = `BC_MEM_READ ; // if this is not burst transfer or memory read line command is disabled - use memory read
|
2'b10: del_bc = `BC_IO_READ ;
|
2'b01: del_bc = `BC_MEM_READ ; // same as previous case
|
2'b01: del_bc = `BC_MEM_READ_LN ;
|
2'b10: del_bc = `BC_MEM_READ_LN ; // burst transfer, memory read line command enabled, prefetch disabled - use memory read line command
|
2'b00: del_bc = `BC_MEM_READ ;
|
2'b11: del_bc = `BC_MEM_READ_MUL ; // same as previous case, except prefetch is enabled - use memory read multiple command
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
end
|
|
|
// WISHBONE data output select lines for output multiplexor
|
reg del_in_progress ; // state machine indicates whether current read completion is in progress on WISHBONE bus
|
reg sdata_o_sel ;
|
|
|
|
reg del_in_progress_out ; // state machine indicates whether current read completion is in progress on WISHBONE bus
|
|
|
|
wire image_access_error = (map && (burst_transfer || sel_error)) || // IO write is a burst or has wrong select lines active= Error
|
wire image_access_error = (map && (burst_transfer || sel_error)) || // IO write is a burst or has wrong select lines active= Error
|
(~map && ~alligned_address) ; // Mem write to nonaligned address = error;
|
(~map && ~alligned_address) ; // Mem write to nonaligned address = error;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
| Line 614... |
Line 632... |
do_iack_req or
|
do_iack_req or
|
do_iack_comp or
|
do_iack_comp or
|
iack_hit or
|
iack_hit or
|
image_access_error or
|
image_access_error or
|
wbw_fifo_almost_full_in or
|
wbw_fifo_almost_full_in or
|
|
wbw_fifo_full_in or
|
do_del_request or
|
do_del_request or
|
wbr_fifo_empty_in
|
wbr_fifo_empty_in
|
)
|
)
|
begin
|
begin
|
// default signal values
|
// default signal values
|
| Line 643... |
Line 662... |
|
|
// configuration space control signals inactive
|
// configuration space control signals inactive
|
conf_wenable = 1'b0 ;
|
conf_wenable = 1'b0 ;
|
conf_renable = 1'b0 ;
|
conf_renable = 1'b0 ;
|
|
|
// WISHBONE data output selection - drive wbr output
|
|
sdata_o_sel = WBR_SEL ;
|
|
|
|
// read is not in progress
|
// read is not in progress
|
del_in_progress_out = 1'b0 ;
|
del_in_progress = 1'b0 ;
|
|
|
decode_en = 1'b0 ;
|
decode_en = 1'b0 ;
|
|
|
wbw_data_out_sel = SEL_ADDR_IN ;
|
wbw_data_out_sel = SEL_ADDR_IN ;
|
|
|
|
sample_address_out = 1'b0 ;
|
|
|
case (c_state)
|
case (c_state)
|
S_IDLE: begin
|
S_IDLE: begin
|
if ( wattempt || rattempt )
|
if ( wattempt || rattempt )
|
begin
|
begin
|
`ifdef WB_DECODE_FAST
|
`ifdef WB_DECODE_FAST
|
decode_en = 1'b1 ;
|
decode_en = 1'b1 ;
|
n_state = S_START ;
|
n_state = S_START ;
|
`else
|
`else
|
n_state = S_DEC1 ;
|
n_state = S_DEC1 ;
|
`endif
|
`endif
|
|
sample_address_out = 1'b1 ;
|
end
|
end
|
else
|
else
|
n_state = S_IDLE ;
|
n_state = S_IDLE ;
|
end
|
end
|
|
|
| Line 694... |
Line 715... |
end
|
end
|
|
|
S_START:begin
|
S_START:begin
|
if (wb_conf_hit) // configuration space hit
|
if (wb_conf_hit) // configuration space hit
|
begin
|
begin
|
|
`ifdef HOST
|
|
wbw_data_out_sel = SEL_CCYC_ADDR ;
|
|
`endif
|
|
|
if ( wattempt )
|
if ( wattempt )
|
n_state = S_CONF_WRITE ; // go to conf. write state
|
n_state = S_CONF_WRITE ; // go to conf. write state
|
else
|
else
|
if ( rattempt )
|
if ( rattempt )
|
begin
|
begin
|
n_state = S_CONF_READ ; // go to conf. read state
|
n_state = S_CONF_READ ; // go to conf. read state
|
if(~(ccyc_hit || iack_hit))
|
|
sdata_o_sel = CONF_SEL ;
|
|
end
|
end
|
else
|
else
|
n_state = S_IDLE ; // master terminated - go back to idle state
|
n_state = S_IDLE ; // master terminated - go back to idle state
|
|
|
end // wb_conf_hit*/
|
end // wb_conf_hit
|
else
|
else
|
if(wb_hit && (wattempt || rattempt))
|
if(wb_hit && (wattempt || rattempt))
|
begin
|
begin
|
|
wbw_data_out_sel = SEL_DATA_IN ;
|
|
|
// check error conditions for image writes or reads
|
// check error conditions for image writes or reads
|
if ( image_access_error )
|
if ( image_access_error )
|
begin
|
begin
|
n_state = S_IDLE ; // go back to idle state because of an error condition
|
n_state = S_IDLE ; // go back to idle state because of an error condition
|
| Line 748... |
Line 772... |
else
|
else
|
begin
|
begin
|
err = wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] ;
|
err = wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] ;
|
ack = ~wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] ;
|
ack = ~wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] ;
|
wbr_fifo_renable = 1'b1 ;
|
wbr_fifo_renable = 1'b1 ;
|
del_in_progress_out = 1'b1 ;
|
del_in_progress = 1'b1 ;
|
|
|
if ( wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT] )
|
if ( wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT] )
|
begin
|
begin
|
|
|
n_state = S_IDLE ; // go back to idle state
|
n_state = S_IDLE ; // go back to idle state
|
| Line 764... |
Line 788... |
n_state = S_READ ; // go to read state
|
n_state = S_READ ; // go to read state
|
end
|
end
|
end
|
end
|
else
|
else
|
n_state = S_IDLE ;
|
n_state = S_IDLE ;
|
|
|
end
|
end
|
|
|
S_W_ADDR_DATA: begin
|
S_W_ADDR_DATA: begin
|
wbw_data_out_sel = SEL_DATA_IN ;
|
wbw_data_out_sel = SEL_DATA_IN ;
|
err = burst_transfer && wattempt && ~alligned_address ;
|
err = burst_transfer && wattempt && ~alligned_address ;
|
rty = burst_transfer && wattempt && wbw_fifo_almost_full_in ;
|
rty = burst_transfer && wattempt && (wbw_fifo_almost_full_in || wbw_fifo_full_in) ;
|
|
|
if ( ~burst_transfer || wattempt && ( ~alligned_address || wbw_fifo_almost_full_in) )
|
if ( ~burst_transfer || wattempt && ( ~alligned_address || wbw_fifo_almost_full_in || wbw_fifo_full_in ) )
|
begin
|
begin
|
n_state = S_IDLE ;
|
n_state = S_IDLE ;
|
|
|
// write last data to FIFO and don't latch new data
|
// write last data to FIFO and don't latch new data
|
wbw_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ;
|
wbw_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ;
|
| Line 793... |
Line 818... |
end
|
end
|
end // S_W_ADDR_DATA
|
end // S_W_ADDR_DATA
|
|
|
S_READ:begin
|
S_READ:begin
|
// this state is for reads only - in this state read is in progress all the time
|
// this state is for reads only - in this state read is in progress all the time
|
del_in_progress_out = 1'b1 ;
|
del_in_progress = 1'b1 ;
|
|
|
ack = burst_transfer && rattempt && ~wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] && alligned_address && ~wbr_fifo_empty_in ;
|
ack = burst_transfer && rattempt && ~wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] && alligned_address && ~wbr_fifo_empty_in ;
|
err = burst_transfer && rattempt && ((wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || ~alligned_address) && ~wbr_fifo_empty_in) ;
|
err = burst_transfer && rattempt && ((wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || ~alligned_address) && ~wbr_fifo_empty_in) ;
|
rty = burst_transfer && rattempt && wbr_fifo_empty_in && alligned_address ;
|
//rty = burst_transfer && rattempt && wbr_fifo_empty_in && alligned_address ;
|
|
|
// if acknowledge is beeing signalled then enable read from wbr fifo
|
// if acknowledge is beeing signalled then enable read from wbr fifo
|
wbr_fifo_renable = burst_transfer && rattempt && alligned_address && ~wbr_fifo_empty_in ;
|
wbr_fifo_renable = burst_transfer && rattempt && alligned_address && ~wbr_fifo_empty_in ;
|
|
|
if ( ~burst_transfer || rattempt && (~alligned_address || wbr_fifo_empty_in || wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT]) )
|
if ( ~burst_transfer || rattempt && (~alligned_address || wbr_fifo_empty_in || wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT]) )
|
begin
|
begin
|
n_state = S_IDLE ;
|
n_state = S_IDLE ;
|
del_done = 1'b1 ;
|
del_done = 1'b1 ;
|
wbr_fifo_flush = ~wbr_fifo_empty_in && ~(wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT]) ;
|
wbr_fifo_flush = ~wbr_fifo_empty_in ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
n_state = S_READ ;
|
n_state = S_READ ;
|
end
|
end
|
end // S_READ
|
end // S_READ
|
|
|
S_CONF_WRITE: begin
|
S_CONF_WRITE: begin
|
`ifdef HOST
|
`ifdef HOST
|
wbw_data_out_sel = SEL_CCYC_ADDR ;
|
wbw_data_out_sel = SEL_CCYC_ADDR ;
|
|
del_req = do_ccyc_req && ~burst_transfer && alligned_address ;
|
|
del_done = do_ccyc_comp && ~burst_transfer && alligned_address ;
|
|
del_in_progress = do_ccyc_comp && ~burst_transfer && alligned_address ;
|
`endif
|
`endif
|
|
|
n_state = S_IDLE ; // next state after configuration access is always idle
|
n_state = S_IDLE ; // next state after configuration access is always idle
|
del_req = do_ccyc_req && ~burst_transfer ;
|
|
del_done = do_ccyc_comp && ~burst_transfer ;
|
|
del_in_progress_out = do_ccyc_comp && ~burst_transfer ;
|
|
|
|
if ( burst_transfer || ~alligned_address )
|
if ( burst_transfer || ~alligned_address )
|
begin
|
begin
|
err = 1'b1 ;
|
err = 1'b1 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
`ifdef HOST
|
if ( do_ccyc_req || (ccyc_hit && ~do_ccyc_comp))
|
if ( do_ccyc_req || (ccyc_hit && ~do_ccyc_comp))
|
begin
|
begin
|
rty = 1'b1 ;
|
rty = 1'b1 ;
|
end
|
end
|
else
|
else
|
| Line 844... |
Line 871... |
else
|
else
|
begin
|
begin
|
ack = ~ccyc_hit ;
|
ack = ~ccyc_hit ;
|
conf_wenable = ~ccyc_hit ;
|
conf_wenable = ~ccyc_hit ;
|
end
|
end
|
|
`else
|
|
ack = 1'b1 ;
|
|
conf_wenable = 1'b1 ;
|
|
`endif
|
end
|
end
|
end // S_CONF_WRITE
|
end // S_CONF_WRITE
|
|
|
S_CONF_READ: begin
|
S_CONF_READ: begin
|
`ifdef HOST
|
`ifdef HOST
|
wbw_data_out_sel = SEL_CCYC_ADDR ;
|
wbw_data_out_sel = SEL_CCYC_ADDR ;
|
|
del_req = ~burst_transfer && alligned_address && ( do_ccyc_req || do_iack_req );
|
|
del_done = ~burst_transfer && alligned_address && ( do_ccyc_comp || do_iack_comp ) ;
|
|
del_in_progress = ~burst_transfer && alligned_address && ( do_ccyc_comp || do_iack_comp ) ;
|
|
wbr_fifo_renable = ~burst_transfer && alligned_address && ( do_ccyc_comp || do_iack_comp ) ;
|
`endif
|
`endif
|
n_state = S_IDLE ; // next state after configuration access is always idle
|
|
del_req = ~burst_transfer && ( do_ccyc_req || do_iack_req );
|
|
del_done = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ;
|
|
del_in_progress_out = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ;
|
|
wbr_fifo_renable = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ;
|
|
|
|
if ( ~(ccyc_hit || iack_hit) )
|
n_state = S_IDLE ; // next state after configuration access is always idle
|
sdata_o_sel = CONF_SEL ;
|
|
|
|
if ( burst_transfer || ~alligned_address )
|
if ( burst_transfer || ~alligned_address )
|
begin
|
begin
|
err = 1'b1 ;
|
err = 1'b1 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
`ifdef HOST
|
if ( do_ccyc_req || ( ccyc_hit && ~do_ccyc_comp ))
|
if ( do_ccyc_req || ( ccyc_hit && ~do_ccyc_comp ))
|
begin
|
begin
|
rty = 1'b1 ;
|
rty = 1'b1 ;
|
end
|
end
|
else
|
else
|
| Line 887... |
Line 916... |
else
|
else
|
begin
|
begin
|
ack = ~( ccyc_hit || iack_hit ) ;
|
ack = ~( ccyc_hit || iack_hit ) ;
|
conf_renable = ~( ccyc_hit || iack_hit ) ;
|
conf_renable = ~( ccyc_hit || iack_hit ) ;
|
end
|
end
|
|
`else
|
|
ack = 1'b1 ;
|
|
conf_renable = 1'b1 ;
|
|
`endif
|
end
|
end
|
|
|
end //S_CONF_READ
|
end //S_CONF_READ
|
default:begin
|
default:begin
|
n_state = S_IDLE ; // return to idle state
|
n_state = S_IDLE ; // return to idle state
|
end //default
|
end //default
|
endcase
|
endcase
|
end
|
end
|
|
|
// configuration space offset output assignment
|
// configuration space offset output assignment
|
assign wb_conf_offset_out = {wb_addr_in[11:2], 2'b00} ; // upper 10 bits of address input and two zeros
|
assign wb_conf_offset_out = {wb_addr_in[11:2], 2'b00} ; // upper 10 bits of address input and two zeros
|
|
|
// Configuration space byte enables output
|
|
assign wb_conf_be_out = SEL_I ; // just route select lines from WISHBONE to conf space
|
|
|
|
// data output assignment - for image writes, first data is address, subsequent data comes from intermediate register
|
// data output assignment - for image writes, first data is address, subsequent data comes from intermediate register
|
reg [31:0] wb_data_out ;
|
reg [31:0] wb_data ;
|
`ifdef HOST
|
`ifdef HOST
|
always@(wbw_data_out_sel or wb_addr_in or ccyc_addr_in or d_incoming)
|
reg [1:0] wbw_data_out_sel_reg ;
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
wbw_data_out_sel_reg <= #`FF_DELAY SEL_ADDR_IN ;
|
|
else
|
|
wbw_data_out_sel_reg <= #`FF_DELAY wbw_data_out_sel ;
|
|
end
|
|
|
|
always@(wbw_data_out_sel_reg or wb_addr_in or ccyc_addr_in or d_incoming)
|
begin
|
begin
|
case ( wbw_data_out_sel )
|
case ( wbw_data_out_sel_reg )
|
SEL_CCYC_ADDR: wb_data_out = ccyc_addr_in ;
|
SEL_CCYC_ADDR: wb_data = ccyc_addr_in ;
|
SEL_DATA_IN: wb_data_out = d_incoming ;
|
SEL_DATA_IN: wb_data = d_incoming ;
|
default: wb_data_out = wb_addr_in ;
|
default: wb_data = wb_addr_in ;
|
endcase
|
endcase
|
end
|
end
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
always@(wbw_data_out_sel or wb_addr_in or d_incoming)
|
reg wbw_data_out_sel_reg ;
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
wbw_data_out_sel_reg <= #`FF_DELAY SEL_ADDR_IN ;
|
|
else
|
|
wbw_data_out_sel_reg <= #`FF_DELAY wbw_data_out_sel ;
|
|
end
|
|
|
|
always@(wbw_data_out_sel_reg or wb_addr_in or d_incoming)
|
begin
|
begin
|
if ( wbw_data_out_sel )
|
if ( wbw_data_out_sel_reg )
|
wb_data_out = wb_addr_in ;
|
wb_data = wb_addr_in ;
|
else
|
else
|
wb_data_out = d_incoming ;
|
wb_data = d_incoming ;
|
end
|
end
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
// command / byte enable assignment - with address, bus command is provided, with data - byte enables are provided
|
// command / byte enable assignment - with address, bus command is provided, with data - byte enables are provided
|
reg [3:0] wb_cbe ;
|
reg [3:0] wb_cbe ;
|
assign wb_cbe_out = wb_cbe ;
|
|
|
|
always@(wbw_data_out_sel or d_incoming or map)
|
always@(wbw_data_out_sel_reg or d_incoming or map)
|
begin
|
begin
|
if (wbw_data_out_sel && map)
|
if (wbw_data_out_sel_reg && map)
|
wb_cbe = `BC_IO_WRITE ;
|
wb_cbe = `BC_IO_WRITE ;
|
else
|
else
|
if (wbw_data_out_sel)
|
if (wbw_data_out_sel_reg)
|
wb_cbe = `BC_MEM_WRITE ;
|
wb_cbe = `BC_MEM_WRITE ;
|
else
|
else
|
wb_cbe = ~(d_incoming[35:32]) ;
|
wb_cbe = ~(d_incoming[35:32]) ;
|
end
|
end
|
|
|
// for configuration writes, data output is always data from WISHBONE - in guest implementation data is all 0.
|
// for configuration writes, data output is always data from WISHBONE - in guest implementation data is all 0.
|
`ifdef GUEST
|
`ifdef GUEST
|
assign wb_conf_data_out = 32'h00000000 ;
|
assign wb_conf_data_out = 32'h00000000 ;
|
|
`endif
|
|
|
|
`ifdef GUEST
|
|
`ifdef NO_CNF_IMAGE
|
|
`else
|
|
`define DO_OUT_MUX
|
|
`endif
|
`else
|
`else
|
`ifdef HOST
|
`ifdef HOST
|
assign wb_conf_data_out = SDATA_I ;
|
`define DO_OUT_MUX ;
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
// WISHBONE data output multiplexor
|
`ifdef DO_OUT_MUX
|
reg [31:0] sdata ;
|
reg [31:0] sdata_source ;
|
assign SDATA_O = sdata ;
|
|
|
// WISHBONE data output select lines for output multiplexor
|
|
wire sdata_o_sel_new = ( wb_conf_hit_in && ~wiack_hit && ~wccyc_hit ) ? CONF_SEL : WBR_SEL ;
|
|
reg sdata_o_sel ;
|
|
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
sdata_o_sel <= #`FF_DELAY WBR_SEL ;
|
|
else
|
|
if ( decode_en )
|
|
sdata_o_sel <= #`FF_DELAY sdata_o_sel_new ;
|
|
end
|
|
|
always@(sdata_o_sel or wbr_fifo_data_in or wb_conf_data_in)
|
always@(sdata_o_sel or wbr_fifo_data_in or wb_conf_data_in)
|
begin
|
begin
|
case (sdata_o_sel)
|
case (sdata_o_sel)
|
WBR_SEL :sdata = wbr_fifo_data_in ;
|
WBR_SEL :sdata_source = wbr_fifo_data_in ;
|
CONF_SEL:sdata = wb_conf_data_in ;
|
CONF_SEL:sdata_source = wb_conf_data_in ;
|
endcase
|
endcase
|
end
|
end
|
|
`undef DO_OUT_MUX
|
|
`else
|
|
wire [31:0] sdata_source = wbr_fifo_data_in ;
|
|
`endif
|
|
|
|
`ifdef REGISTER_WBS_OUTPUTS
|
|
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
begin
|
|
ACK_O <= #`FF_DELAY 1'b0 ;
|
|
RTY_O <= #`FF_DELAY 1'b0 ;
|
|
ERR_O <= #`FF_DELAY 1'b0 ;
|
|
SDATA_O <= #`FF_DELAY 0 ;
|
|
del_write_out <= #`FF_DELAY 1'b0 ;
|
|
|
|
`ifdef HOST
|
|
wb_conf_wenable_out <= #`FF_DELAY 1'b0 ;
|
|
wb_conf_data_out <= #`FF_DELAY 0 ;
|
|
`endif
|
|
|
|
del_bc_out <= #`FF_DELAY `BC_RESERVED0 ;
|
|
del_req_out <= #`FF_DELAY 1'b0 ;
|
|
del_done_out <= #`FF_DELAY 1'b0 ;
|
|
del_burst_out <= #`FF_DELAY 1'b0 ;
|
|
del_in_progress_out <= #`FF_DELAY 1'b0 ;
|
|
wb_conf_be_out <= #`FF_DELAY 0 ;
|
|
wb_data_out <= #`FF_DELAY 0 ;
|
|
wb_cbe_out <= #`FF_DELAY 0 ;
|
|
wbw_fifo_wenable_out <= #`FF_DELAY 0 ;
|
|
wbw_fifo_control_out <= #`FF_DELAY 0 ;
|
|
wbr_fifo_renable_out <= #`FF_DELAY 0 ;
|
|
end
|
|
else
|
|
begin
|
|
ACK_O <= #`FF_DELAY ack && !ACK_O ;
|
|
RTY_O <= #`FF_DELAY rty && !RTY_O ;
|
|
ERR_O <= #`FF_DELAY err && !ERR_O ;
|
|
SDATA_O <= #`FF_DELAY sdata_source ;
|
|
del_write_out <= #`FF_DELAY WE_I ;
|
|
|
|
`ifdef HOST
|
|
wb_conf_wenable_out <= #`FF_DELAY conf_wenable ;
|
|
wb_conf_data_out <= #`FF_DELAY SDATA_I ;
|
|
`endif
|
|
|
|
del_bc_out <= #`FF_DELAY del_bc ;
|
|
del_req_out <= #`FF_DELAY del_req ;
|
|
del_done_out <= #`FF_DELAY del_done ;
|
|
del_burst_out <= #`FF_DELAY del_burst ;
|
|
del_in_progress_out <= #`FF_DELAY del_in_progress ;
|
|
wb_conf_be_out <= #`FF_DELAY SEL_I ;
|
|
wb_data_out <= #`FF_DELAY wb_data ;
|
|
wb_cbe_out <= #`FF_DELAY wb_cbe ;
|
|
wbw_fifo_wenable_out <= #`FF_DELAY wbw_fifo_wenable ;
|
|
wbw_fifo_control_out <= #`FF_DELAY wbw_fifo_control ;
|
|
wbr_fifo_renable_out <= #`FF_DELAY wbr_fifo_renable ;
|
|
end
|
|
end
|
|
|
|
`else
|
|
|
|
assign SDATA_O = sdata_source ;
|
|
|
|
assign ACK_O = ack ;
|
|
assign RTY_O = rty ;
|
|
assign ERR_O = err ;
|
|
|
|
// write operation indicator for delayed transaction requests
|
|
assign del_write_out = WE_I ;
|
|
assign del_bc_out = del_bc ;
|
|
assign del_req_out = del_req ; // read request
|
|
assign del_done_out = del_done ; // read done
|
|
assign del_burst_out = del_burst ;
|
|
assign del_in_progress_out = del_in_progress ;
|
|
`ifdef HOST
|
|
assign wb_conf_data_out = SDATA_I ;
|
|
assign wb_conf_wenable_out = conf_wenable ;
|
|
`endif
|
|
// Configuration space byte enables output
|
|
assign wb_conf_be_out = SEL_I ; // just route select lines from WISHBONE to conf space
|
|
assign wb_data_out = wb_data ;
|
|
assign wb_cbe_out = wb_cbe ;
|
|
assign wbw_fifo_wenable_out = wbw_fifo_wenable ; //write enable for WBW_FIFO
|
|
assign wbw_fifo_control_out = wbw_fifo_control ; //control bus output for WBW_FIFO
|
|
assign wbr_fifo_renable_out = wbr_fifo_renable ; //read enable for wbr_fifo
|
|
`endif
|
|
|
endmodule //WB_SLAVE
|
endmodule //WB_SLAVE
|
|
|
No newline at end of file
|
No newline at end of file
|
