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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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Line 545... |
// wire for write attempt - 1 when external WB master is attempting a write
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// wire for write attempt - 1 when external WB master is attempting a write
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// wire for read attempt - 1 when external master is attempting a read
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// wire for read attempt - 1 when external master is attempting a read
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wire wattempt = ( CYC_I && STB_I && WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ;
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wire wattempt = ( CYC_I && STB_I && WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ;
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wire rattempt = ( CYC_I && STB_I && ~WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ;
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wire rattempt = ( CYC_I && STB_I && ~WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ;
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`ifdef WB_DECODE_FAST
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`undef WB_DECODE_FAST
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`define WB_DECODE_MEDIUM
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`endif
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`else
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`else
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// wire for write attempt - 1 when external WB master is attempting a write
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// wire for write attempt - 1 when external WB master is attempting a write
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// wire for read attempt - 1 when external master is attempting a read
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// wire for read attempt - 1 when external master is attempting a read
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wire wattempt = ( CYC_I && STB_I && WE_I ) ; // write is qualified when cycle, strobe and write enable inputs are all high
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wire wattempt = ( CYC_I && STB_I && WE_I ) ; // write is qualified when cycle, strobe and write enable inputs are all high
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wire rattempt = ( CYC_I && STB_I && ~WE_I ) ; // read is qualified when cycle and strobe are high and write enable is low
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wire rattempt = ( CYC_I && STB_I && ~WE_I ) ; // read is qualified when cycle and strobe are high and write enable is low
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| Line 610... |
Line 608... |
parameter SEL_ADDR_IN = 1'b1 ;
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parameter SEL_ADDR_IN = 1'b1 ;
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parameter SEL_DATA_IN = 1'b0 ;
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parameter SEL_DATA_IN = 1'b0 ;
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`endif
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`endif
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`endif
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`endif
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`ifdef WB_DECODE_FAST
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`ifdef REGISTER_WBS_OUTPUTS
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`define PCI_WB_SLAVE_S_DEC1
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`endif
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`endif
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`ifdef WB_DECODE_MEDIUM
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`define PCI_WB_SLAVE_S_DEC1
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`endif
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`ifdef WB_DECODE_SLOW
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`define PCI_WB_SLAVE_S_DEC1
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`define PCI_WB_SLAVE_S_DEC2
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`endif
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// state machine logic
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// state machine logic
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always@(
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always@(
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c_state or
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c_state or
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wattempt or
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wattempt or
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img_wallow or
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img_wallow or
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| Line 675... |
Line 687... |
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case (c_state)
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case (c_state)
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S_IDLE: begin
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S_IDLE: begin
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if ( wattempt || rattempt )
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if ( wattempt || rattempt )
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begin
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begin
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`ifdef WB_DECODE_FAST
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`ifdef PCI_WB_SLAVE_S_DEC1
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n_state = S_DEC1 ;
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`else
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decode_en = 1'b1 ;
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decode_en = 1'b1 ;
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n_state = S_START ;
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n_state = S_START ;
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`else
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n_state = S_DEC1 ;
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`endif
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`endif
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sample_address_out = 1'b1 ;
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sample_address_out = 1'b1 ;
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end
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end
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else
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else
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n_state = S_IDLE ;
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n_state = S_IDLE ;
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end
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end
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`ifdef PCI_WB_SLAVE_S_DEC1
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S_DEC1: begin
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S_DEC1: begin
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if ( wattempt || rattempt )
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if ( wattempt || rattempt )
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begin
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begin
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`ifdef WB_DECODE_MEDIUM
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`ifdef PCI_WB_SLAVE_S_DEC2
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n_state = S_DEC2 ;
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`else
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decode_en = 1'b1 ;
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decode_en = 1'b1 ;
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n_state = S_START ;
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n_state = S_START ;
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`else
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n_state = S_DEC2 ;
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`endif
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`endif
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end
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end
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else
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else
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n_state = S_IDLE ;
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n_state = S_IDLE ;
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end
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end
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`endif
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`ifdef PCI_WB_SLAVE_S_DEC2
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S_DEC2: begin
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S_DEC2: begin
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if ( wattempt || rattempt )
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if ( wattempt || rattempt )
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begin
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begin
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decode_en = 1'b1 ;
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decode_en = 1'b1 ;
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n_state = S_START ;
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n_state = S_START ;
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end
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end
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else
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else
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n_state = S_IDLE ;
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n_state = S_IDLE ;
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end
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end
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`endif
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S_START:begin
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S_START:begin
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if (wb_conf_hit) // configuration space hit
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if (wb_conf_hit) // configuration space hit
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begin
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begin
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`ifdef HOST
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`ifdef HOST
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wbw_data_out_sel = SEL_CCYC_ADDR ;
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wbw_data_out_sel = SEL_CCYC_ADDR ;
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| Line 994... |
Line 1011... |
`endif
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`endif
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`ifdef GUEST
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`ifdef GUEST
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`ifdef NO_CNF_IMAGE
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`ifdef NO_CNF_IMAGE
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`else
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`else
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`define DO_OUT_MUX
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`define PCI_WB_SLAVE_DO_OUT_MUX
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`endif
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`endif
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`else
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`else
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`ifdef HOST
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`ifdef HOST
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`define DO_OUT_MUX ;
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`define PCI_WB_SLAVE_DO_OUT_MUX ;
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`endif
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`endif
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`endif
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`endif
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`ifdef DO_OUT_MUX
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`ifdef PCI_WB_SLAVE_DO_OUT_MUX
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reg [31:0] sdata_source ;
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reg [31:0] sdata_source ;
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// WISHBONE data output select lines for output multiplexor
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// WISHBONE data output select lines for output multiplexor
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wire sdata_o_sel_new = ( wb_conf_hit_in && ~wiack_hit && ~wccyc_hit ) ? CONF_SEL : WBR_SEL ;
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wire sdata_o_sel_new = ( wb_conf_hit_in && ~wiack_hit && ~wccyc_hit ) ? CONF_SEL : WBR_SEL ;
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reg sdata_o_sel ;
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reg sdata_o_sel ;
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Line 1042... |
case (sdata_o_sel)
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case (sdata_o_sel)
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WBR_SEL :sdata_source = wbr_fifo_data_in ;
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WBR_SEL :sdata_source = wbr_fifo_data_in ;
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CONF_SEL:sdata_source = wb_conf_data_in ;
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CONF_SEL:sdata_source = wb_conf_data_in ;
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endcase
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endcase
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end
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end
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`undef DO_OUT_MUX
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`else
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`else
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wire [31:0] sdata_source = wbr_fifo_data_in ;
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wire [31:0] sdata_source = wbr_fifo_data_in ;
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`endif
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`endif
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`ifdef REGISTER_WBS_OUTPUTS
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`ifdef REGISTER_WBS_OUTPUTS
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