| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:30 mihad
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|
// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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|
|
// Module instantiates and connects other modules lower in hierarcy
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// Module instantiates and connects other modules lower in hierarcy
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// Wishbone slave unit consists of modules that together form datapath
|
// Wishbone slave unit consists of modules that together form datapath
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// between external WISHBONE masters and external PCI targets
|
// between external WISHBONE masters and external PCI targets
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`include "constants.v"
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`include "pci_constants.v"
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|
|
|
// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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|
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module WB_SLAVE_UNIT
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module WB_SLAVE_UNIT
|
(
|
(
|
reset_in,
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reset_in,
|
wb_clock_in,
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wb_clock_in,
|
pci_clock_in,
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pci_clock_in,
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| Line 93... |
Line 100... |
wbu_ta4_in,
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wbu_ta4_in,
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wbu_ta5_in,
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wbu_ta5_in,
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wbu_at_en_in,
|
wbu_at_en_in,
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wbu_ccyc_addr_in ,
|
wbu_ccyc_addr_in ,
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wbu_master_enable_in,
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wbu_master_enable_in,
|
|
wbu_cache_line_size_not_zero,
|
wbu_cache_line_size_in,
|
wbu_cache_line_size_in,
|
wbu_pciif_gnt_in,
|
wbu_pciif_gnt_in,
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wbu_pciif_frame_in,
|
wbu_pciif_frame_in,
|
wbu_pciif_irdy_in,
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wbu_pciif_irdy_in,
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wbu_pciif_trdy_in,
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wbu_pciif_trdy_in,
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| Line 121... |
Line 129... |
wbu_err_addr_out,
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wbu_err_addr_out,
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wbu_err_bc_out,
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wbu_err_bc_out,
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wbu_err_signal_out,
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wbu_err_signal_out,
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wbu_err_source_out,
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wbu_err_source_out,
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wbu_err_rty_exp_out,
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wbu_err_rty_exp_out,
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wbu_err_pending_in,
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wbu_tabort_rec_out,
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wbu_tabort_rec_out,
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wbu_mabort_rec_out,
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wbu_mabort_rec_out,
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wbu_conf_offset_out,
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wbu_conf_offset_out,
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wbu_conf_renable_out,
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wbu_conf_renable_out,
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wbu_conf_wenable_out,
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wbu_conf_wenable_out,
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wbu_conf_be_out,
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wbu_conf_be_out,
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wbu_conf_data_out,
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wbu_conf_data_out,
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wbu_del_read_comp_pending_out,
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wbu_del_read_comp_pending_out,
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wbu_wbw_fifo_empty_out,
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wbu_wbw_fifo_empty_out,
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wbu_latency_tim_val_in,
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wbu_latency_tim_val_in,
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wbu_pciif_load_next_out
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wbu_ad_load_out,
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|
wbu_ad_load_on_transfer_out
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);
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);
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|
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input reset_in,
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input reset_in,
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wb_clock_in,
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wb_clock_in,
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pci_clock_in ;
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pci_clock_in ;
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| Line 185... |
Line 193... |
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input [23:0] wbu_ccyc_addr_in ;
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input [23:0] wbu_ccyc_addr_in ;
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|
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input wbu_master_enable_in ;
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input wbu_master_enable_in ;
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|
|
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input wbu_cache_line_size_not_zero ;
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input [7:0] wbu_cache_line_size_in ;
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input [7:0] wbu_cache_line_size_in ;
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|
|
input wbu_pciif_gnt_in ;
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input wbu_pciif_gnt_in ;
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input wbu_pciif_frame_in ;
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input wbu_pciif_frame_in ;
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input wbu_pciif_frame_en_in ;
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input wbu_pciif_frame_en_in ;
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| Line 216... |
Line 225... |
output [31:0] wbu_err_addr_out ;
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output [31:0] wbu_err_addr_out ;
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output [3:0] wbu_err_bc_out ;
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output [3:0] wbu_err_bc_out ;
|
output wbu_err_signal_out ;
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output wbu_err_signal_out ;
|
output wbu_err_source_out ;
|
output wbu_err_source_out ;
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output wbu_err_rty_exp_out ;
|
output wbu_err_rty_exp_out ;
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input wbu_err_pending_in ;
|
|
output wbu_tabort_rec_out ;
|
output wbu_tabort_rec_out ;
|
output wbu_mabort_rec_out ;
|
output wbu_mabort_rec_out ;
|
|
|
output [11:0] wbu_conf_offset_out ;
|
output [11:0] wbu_conf_offset_out ;
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output wbu_conf_renable_out ;
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output wbu_conf_renable_out ;
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| Line 231... |
Line 239... |
output wbu_del_read_comp_pending_out ;
|
output wbu_del_read_comp_pending_out ;
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output wbu_wbw_fifo_empty_out ;
|
output wbu_wbw_fifo_empty_out ;
|
|
|
input [7:0] wbu_latency_tim_val_in ;
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input [7:0] wbu_latency_tim_val_in ;
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|
|
output wbu_pciif_load_next_out ;
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output wbu_ad_load_out ;
|
|
output wbu_ad_load_on_transfer_out ;
|
|
|
|
|
// pci master interface outputs
|
// pci master interface outputs
|
wire [31:0] pcim_if_address_out ;
|
wire [31:0] pcim_if_address_out ;
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wire [3:0] pcim_if_bc_out ;
|
wire [3:0] pcim_if_bc_out ;
|
wire [31:0] pcim_if_data_out ;
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wire [31:0] pcim_if_data_out ;
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| Line 259... |
Line 269... |
wire pcim_if_tabort_out ;
|
wire pcim_if_tabort_out ;
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wire pcim_if_mabort_out ;
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wire pcim_if_mabort_out ;
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wire [31:0] pcim_if_next_data_out ;
|
wire [31:0] pcim_if_next_data_out ;
|
wire [3:0] pcim_if_next_be_out ;
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wire [3:0] pcim_if_next_be_out ;
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wire pcim_if_next_last_out ;
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wire pcim_if_next_last_out ;
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wire pcim_if_posted_write_not_present_out ;
|
|
|
|
|
|
|
wire pcim_sm_req_out ;
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wire pcim_sm_req_out ;
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wire pcim_sm_frame_out ;
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wire pcim_sm_frame_out ;
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| Line 271... |
Line 282... |
wire pcim_sm_irdy_en_out ;
|
wire pcim_sm_irdy_en_out ;
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wire [31:0] pcim_sm_ad_out ;
|
wire [31:0] pcim_sm_ad_out ;
|
wire pcim_sm_ad_en_out ;
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wire pcim_sm_ad_en_out ;
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wire [3:0] pcim_sm_cbe_out ;
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wire [3:0] pcim_sm_cbe_out ;
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wire pcim_sm_cbe_en_out ;
|
wire pcim_sm_cbe_en_out ;
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wire pcim_sm_load_next_out ;
|
wire pcim_sm_ad_load_out ;
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wire pcim_sm_ad_load_on_transfer_out ;
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|
|
wire pcim_sm_wait_out ;
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wire pcim_sm_wait_out ;
|
wire pcim_sm_wtransfer_out ;
|
wire pcim_sm_wtransfer_out ;
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wire pcim_sm_rtransfer_out ;
|
wire pcim_sm_rtransfer_out ;
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wire pcim_sm_retry_out ;
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wire pcim_sm_retry_out ;
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wire pcim_sm_werror_out ;
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wire pcim_sm_rerror_out ;
|
wire pcim_sm_rerror_out ;
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wire pcim_sm_first_out ;
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wire pcim_sm_first_out ;
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wire pcim_sm_mabort_out ;
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wire pcim_sm_mabort_out ;
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wire pcim_sm_frame_load_out ;
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wire pcim_sm_frame_load_out ;
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|
|
| Line 293... |
Line 304... |
assign wbu_err_source_out = pcim_if_err_source_out ;
|
assign wbu_err_source_out = pcim_if_err_source_out ;
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assign wbu_err_rty_exp_out = pcim_if_err_rty_exp_out ;
|
assign wbu_err_rty_exp_out = pcim_if_err_rty_exp_out ;
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assign wbu_tabort_rec_out = pcim_if_tabort_out ;
|
assign wbu_tabort_rec_out = pcim_if_tabort_out ;
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assign wbu_mabort_rec_out = pcim_if_mabort_out ;
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assign wbu_mabort_rec_out = pcim_if_mabort_out ;
|
|
|
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assign wbu_wbw_fifo_empty_out = pcim_if_posted_write_not_present_out ;
|
|
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// pci master state machine outputs
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// pci master state machine outputs
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// pci interface signals
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// pci interface signals
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assign wbu_pciif_req_out = pcim_sm_req_out ;
|
assign wbu_pciif_req_out = pcim_sm_req_out ;
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assign wbu_pciif_frame_out = pcim_sm_frame_out ;
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assign wbu_pciif_frame_out = pcim_sm_frame_out ;
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assign wbu_pciif_frame_en_out = pcim_sm_frame_en_out ;
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assign wbu_pciif_frame_en_out = pcim_sm_frame_en_out ;
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| Line 304... |
Line 317... |
assign wbu_pciif_irdy_en_out = pcim_sm_irdy_en_out ;
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assign wbu_pciif_irdy_en_out = pcim_sm_irdy_en_out ;
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assign wbu_pciif_ad_out = pcim_sm_ad_out ;
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assign wbu_pciif_ad_out = pcim_sm_ad_out ;
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assign wbu_pciif_ad_en_out = pcim_sm_ad_en_out ;
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assign wbu_pciif_ad_en_out = pcim_sm_ad_en_out ;
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assign wbu_pciif_cbe_out = pcim_sm_cbe_out ;
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assign wbu_pciif_cbe_out = pcim_sm_cbe_out ;
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assign wbu_pciif_cbe_en_out = pcim_sm_cbe_en_out ;
|
assign wbu_pciif_cbe_en_out = pcim_sm_cbe_en_out ;
|
assign wbu_pciif_load_next_out = pcim_sm_load_next_out ;
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assign wbu_ad_load_out = pcim_sm_ad_load_out ;
|
|
assign wbu_ad_load_on_transfer_out = pcim_sm_ad_load_on_transfer_out ;
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|
|
// signals to internal of the core
|
// signals to internal of the core
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wire [31:0] pcim_sm_data_out ;
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wire [31:0] pcim_sm_data_out ;
|
|
|
// wishbone slave state machine outputs
|
// wishbone slave state machine outputs
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| Line 331... |
Line 345... |
wire wbs_sm_del_in_progress_out ;
|
wire wbs_sm_del_in_progress_out ;
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wire [31:0] wbs_sm_sdata_out ;
|
wire [31:0] wbs_sm_sdata_out ;
|
wire wbs_sm_ack_out ;
|
wire wbs_sm_ack_out ;
|
wire wbs_sm_rty_out ;
|
wire wbs_sm_rty_out ;
|
wire wbs_sm_err_out ;
|
wire wbs_sm_err_out ;
|
|
wire wbs_sm_sample_address_out ;
|
|
|
assign wbu_conf_offset_out = wbs_sm_conf_offset_out ;
|
assign wbu_conf_offset_out = wbs_sm_conf_offset_out ;
|
assign wbu_conf_renable_out = wbs_sm_conf_renable_out ;
|
assign wbu_conf_renable_out = wbs_sm_conf_renable_out ;
|
assign wbu_conf_wenable_out = wbs_sm_conf_wenable_out ;
|
assign wbu_conf_wenable_out = wbs_sm_conf_wenable_out ;
|
assign wbu_conf_be_out = ~wbs_sm_conf_be_out ;
|
assign wbu_conf_be_out = ~wbs_sm_conf_be_out ;
|
| Line 355... |
Line 370... |
wire fifos_wbw_almost_full_out ;
|
wire fifos_wbw_almost_full_out ;
|
wire fifos_wbw_full_out ;
|
wire fifos_wbw_full_out ;
|
wire fifos_wbw_empty_out ;
|
wire fifos_wbw_empty_out ;
|
wire fifos_wbw_transaction_ready_out ;
|
wire fifos_wbw_transaction_ready_out ;
|
|
|
assign wbu_wbw_fifo_empty_out = fifos_wbw_empty_out ;
|
|
|
|
// wbr_fifo_outputs
|
// wbr_fifo_outputs
|
wire [31:0] fifos_wbr_data_out ;
|
wire [31:0] fifos_wbr_data_out ;
|
wire [3:0] fifos_wbr_be_out ;
|
wire [3:0] fifos_wbr_be_out ;
|
wire [3:0] fifos_wbr_control_out ;
|
wire [3:0] fifos_wbr_control_out ;
|
wire fifos_wbr_empty_out ;
|
wire fifos_wbr_empty_out ;
|
| Line 412... |
Line 425... |
wire [3:0] wbs_sm_wbr_be_in = fifos_wbr_be_out ;
|
wire [3:0] wbs_sm_wbr_be_in = fifos_wbr_be_out ;
|
wire [31:0] wbs_sm_wbr_data_in = fifos_wbr_data_out ;
|
wire [31:0] wbs_sm_wbr_data_in = fifos_wbr_data_out ;
|
wire [3:0] wbs_sm_wbr_control_in = fifos_wbr_control_out ;
|
wire [3:0] wbs_sm_wbr_control_in = fifos_wbr_control_out ;
|
wire wbs_sm_wbr_empty_in = fifos_wbr_empty_out ;
|
wire wbs_sm_wbr_empty_in = fifos_wbr_empty_out ;
|
wire wbs_sm_pciw_empty_in = wbu_pciw_empty_in ;
|
wire wbs_sm_pciw_empty_in = wbu_pciw_empty_in ;
|
wire wbs_sm_lock_in = ~wbu_master_enable_in || wbu_err_pending_in ;
|
wire wbs_sm_lock_in = ~wbu_master_enable_in ;
|
|
wire wbs_sm_cache_line_size_not_zero = wbu_cache_line_size_not_zero ;
|
wire wbs_sm_cyc_in = CYC_I ;
|
wire wbs_sm_cyc_in = CYC_I ;
|
wire wbs_sm_stb_in = STB_I ;
|
wire wbs_sm_stb_in = STB_I ;
|
wire wbs_sm_we_in = WE_I ;
|
wire wbs_sm_we_in = WE_I ;
|
wire [3:0] wbs_sm_sel_in = SEL_I ;
|
wire [3:0] wbs_sm_sel_in = SEL_I ;
|
wire [31:0] wbs_sm_sdata_in = SDATA_I ;
|
wire [31:0] wbs_sm_sdata_in = SDATA_I ;
|
| Line 464... |
Line 478... |
.wbr_fifo_control_in (wbs_sm_wbr_control_in),
|
.wbr_fifo_control_in (wbs_sm_wbr_control_in),
|
.wbr_fifo_flush_out (wbs_sm_wbr_flush_out),
|
.wbr_fifo_flush_out (wbs_sm_wbr_flush_out),
|
.wbr_fifo_empty_in (wbs_sm_wbr_empty_in),
|
.wbr_fifo_empty_in (wbs_sm_wbr_empty_in),
|
.pciw_fifo_empty_in (wbs_sm_pciw_empty_in),
|
.pciw_fifo_empty_in (wbs_sm_pciw_empty_in),
|
.wbs_lock_in (wbs_sm_lock_in),
|
.wbs_lock_in (wbs_sm_lock_in),
|
|
.cache_line_size_not_zero (wbs_sm_cache_line_size_not_zero),
|
.del_in_progress_out (wbs_sm_del_in_progress_out),
|
.del_in_progress_out (wbs_sm_del_in_progress_out),
|
.ccyc_addr_in (wbs_sm_ccyc_addr_in),
|
.ccyc_addr_in (wbs_sm_ccyc_addr_in),
|
|
.sample_address_out (wbs_sm_sample_address_out),
|
.CYC_I (wbs_sm_cyc_in),
|
.CYC_I (wbs_sm_cyc_in),
|
.STB_I (wbs_sm_stb_in),
|
.STB_I (wbs_sm_stb_in),
|
.WE_I (wbs_sm_we_in),
|
.WE_I (wbs_sm_we_in),
|
.SEL_I (wbs_sm_sel_in),
|
.SEL_I (wbs_sm_sel_in),
|
.SDATA_I (wbs_sm_sdata_in),
|
.SDATA_I (wbs_sm_sdata_in),
|
| Line 526... |
Line 542... |
.wbr_flush_in (fifos_wbr_flush_in),
|
.wbr_flush_in (fifos_wbr_flush_in),
|
.wbr_empty_out (fifos_wbr_empty_out)
|
.wbr_empty_out (fifos_wbr_empty_out)
|
) ;
|
) ;
|
|
|
wire [31:0] amux_addr_in = ADDR_I ;
|
wire [31:0] amux_addr_in = ADDR_I ;
|
|
wire amux_sample_address_in = wbs_sm_sample_address_out ;
|
|
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar0_in = wbu_bar0_in ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar0_in = wbu_bar0_in ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar1_in = wbu_bar1_in ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar1_in = wbu_bar1_in ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar2_in = wbu_bar2_in ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar2_in = wbu_bar2_in ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar3_in = wbu_bar3_in ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar3_in = wbu_bar3_in ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar4_in = wbu_bar4_in ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar4_in = wbu_bar4_in ;
|
| Line 548... |
Line 566... |
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta5_in = wbu_ta5_in ;
|
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta5_in = wbu_ta5_in ;
|
wire [5:0] amux_at_en_in = wbu_at_en_in ;
|
wire [5:0] amux_at_en_in = wbu_at_en_in ;
|
|
|
WB_ADDR_MUX wb_addr_dec
|
WB_ADDR_MUX wb_addr_dec
|
(
|
(
|
|
`ifdef REGISTER_WBS_OUTPUTS
|
|
.clk_in (wb_clock_in),
|
|
.reset_in (reset_in),
|
|
.sample_address_in (amux_sample_address_in),
|
|
`endif
|
.address_in (amux_addr_in),
|
.address_in (amux_addr_in),
|
.bar0_in (amux_bar0_in),
|
.bar0_in (amux_bar0_in),
|
.bar1_in (amux_bar1_in),
|
.bar1_in (amux_bar1_in),
|
.bar2_in (amux_bar2_in),
|
.bar2_in (amux_bar2_in),
|
.bar3_in (amux_bar3_in),
|
.bar3_in (amux_bar3_in),
|
| Line 656... |
Line 679... |
wire [31:0] pcim_if_del_addr_in = del_sync_addr_out ;
|
wire [31:0] pcim_if_del_addr_in = del_sync_addr_out ;
|
wire [3:0] pcim_if_del_bc_in = del_sync_bc_out ;
|
wire [3:0] pcim_if_del_bc_in = del_sync_bc_out ;
|
wire [3:0] pcim_if_del_be_in = del_sync_be_out ;
|
wire [3:0] pcim_if_del_be_in = del_sync_be_out ;
|
wire pcim_if_del_burst_in = del_sync_burst_out ;
|
wire pcim_if_del_burst_in = del_sync_burst_out ;
|
wire pcim_if_del_we_in = del_sync_we_out ;
|
wire pcim_if_del_we_in = del_sync_we_out ;
|
wire pcim_if_err_pending_in = wbu_err_pending_in ;
|
|
wire [7:0] pcim_if_cache_line_size_in = wbu_cache_line_size_in ;
|
wire [7:0] pcim_if_cache_line_size_in = wbu_cache_line_size_in ;
|
wire pcim_if_wait_in = pcim_sm_wait_out ;
|
wire pcim_if_wait_in = pcim_sm_wait_out ;
|
wire pcim_if_wtransfer_in = pcim_sm_wtransfer_out ;
|
wire pcim_if_wtransfer_in = pcim_sm_wtransfer_out ;
|
wire pcim_if_rtransfer_in = pcim_sm_rtransfer_out ;
|
wire pcim_if_rtransfer_in = pcim_sm_rtransfer_out ;
|
wire pcim_if_retry_in = pcim_sm_retry_out ;
|
wire pcim_if_retry_in = pcim_sm_retry_out ;
|
wire pcim_if_werror_in = pcim_sm_werror_out ;
|
|
wire pcim_if_rerror_in = pcim_sm_rerror_out ;
|
wire pcim_if_rerror_in = pcim_sm_rerror_out ;
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wire pcim_if_first_in = pcim_sm_first_out ;
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wire pcim_if_first_in = pcim_sm_first_out ;
|
wire pcim_if_mabort_in = pcim_sm_mabort_out ;
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wire pcim_if_mabort_in = pcim_sm_mabort_out ;
|
|
|
PCI_MASTER32_SM_IF pci_initiator_if
|
PCI_MASTER32_SM_IF pci_initiator_if
|
| Line 703... |
Line 724... |
.del_we_in (pcim_if_del_we_in),
|
.del_we_in (pcim_if_del_we_in),
|
.err_addr_out (pcim_if_err_addr_out),
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.err_addr_out (pcim_if_err_addr_out),
|
.err_bc_out (pcim_if_err_bc_out),
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.err_bc_out (pcim_if_err_bc_out),
|
.err_signal_out (pcim_if_err_signal_out),
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.err_signal_out (pcim_if_err_signal_out),
|
.err_source_out (pcim_if_err_source_out),
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.err_source_out (pcim_if_err_source_out),
|
.err_pending_in (pcim_if_err_pending_in),
|
|
.err_rty_exp_out (pcim_if_err_rty_exp_out),
|
.err_rty_exp_out (pcim_if_err_rty_exp_out),
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.cache_line_size_in (pcim_if_cache_line_size_in),
|
.cache_line_size_in (pcim_if_cache_line_size_in),
|
.mabort_received_out (pcim_if_tabort_out),
|
.mabort_received_out (pcim_if_mabort_out),
|
.tabort_received_out (pcim_if_mabort_out),
|
.tabort_received_out (pcim_if_tabort_out),
|
.next_data_out (pcim_if_next_data_out),
|
.next_data_out (pcim_if_next_data_out),
|
.next_be_out (pcim_if_next_be_out),
|
.next_be_out (pcim_if_next_be_out),
|
.next_last_out (pcim_if_next_last_out),
|
.next_last_out (pcim_if_next_last_out),
|
.wait_in (pcim_if_wait_in),
|
.wait_in (pcim_if_wait_in),
|
.wtransfer_in (pcim_if_wtransfer_in),
|
.wtransfer_in (pcim_if_wtransfer_in),
|
.rtransfer_in (pcim_if_rtransfer_in),
|
.rtransfer_in (pcim_if_rtransfer_in),
|
.retry_in (pcim_if_retry_in),
|
.retry_in (pcim_if_retry_in),
|
.werror_in (pcim_if_werror_in),
|
|
.rerror_in (pcim_if_rerror_in),
|
.rerror_in (pcim_if_rerror_in),
|
.first_in (pcim_if_first_in),
|
.first_in (pcim_if_first_in),
|
.mabort_in (pcim_if_mabort_in)
|
.mabort_in (pcim_if_mabort_in),
|
|
.posted_write_not_present_out (pcim_if_posted_write_not_present_out)
|
);
|
);
|
|
|
// pci master state machine inputs
|
// pci master state machine inputs
|
wire pcim_sm_gnt_in = wbu_pciif_gnt_in ;
|
wire pcim_sm_gnt_in = wbu_pciif_gnt_in ;
|
wire pcim_sm_frame_in = wbu_pciif_frame_in ;
|
wire pcim_sm_frame_in = wbu_pciif_frame_in ;
|
| Line 784... |
Line 804... |
.last_in (pcim_sm_last_in),
|
.last_in (pcim_sm_last_in),
|
.latency_tim_val_in (pcim_sm_latency_tim_val_in),
|
.latency_tim_val_in (pcim_sm_latency_tim_val_in),
|
.next_data_in (pcim_sm_next_data_in),
|
.next_data_in (pcim_sm_next_data_in),
|
.next_be_in (pcim_sm_next_be_in),
|
.next_be_in (pcim_sm_next_be_in),
|
.next_last_in (pcim_sm_next_last_in),
|
.next_last_in (pcim_sm_next_last_in),
|
.load_next_out (pcim_sm_load_next_out),
|
.ad_load_out (pcim_sm_ad_load_out),
|
|
.ad_load_on_transfer_out (pcim_sm_ad_load_on_transfer_out),
|
.wait_out (pcim_sm_wait_out),
|
.wait_out (pcim_sm_wait_out),
|
.wtransfer_out (pcim_sm_wtransfer_out),
|
.wtransfer_out (pcim_sm_wtransfer_out),
|
.rtransfer_out (pcim_sm_rtransfer_out),
|
.rtransfer_out (pcim_sm_rtransfer_out),
|
.retry_out (pcim_sm_retry_out),
|
.retry_out (pcim_sm_retry_out),
|
.werror_out (pcim_sm_werror_out),
|
|
.rerror_out (pcim_sm_rerror_out),
|
.rerror_out (pcim_sm_rerror_out),
|
.first_out (pcim_sm_first_out),
|
.first_out (pcim_sm_first_out),
|
.mabort_out (pcim_sm_mabort_out)
|
.mabort_out (pcim_sm_mabort_out)
|
) ;
|
) ;
|
|
|
endmodule
|
endmodule
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No newline at end of file
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|
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No newline at end of file
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No newline at end of file
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