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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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Line 504... |
wire fifos_wbw_wenable_in = wbs_sm_wbw_wenable_out;
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wire fifos_wbw_wenable_in = wbs_sm_wbw_wenable_out;
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wire [31:0] fifos_wbw_addr_data_in = wbs_sm_data_out ;
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wire [31:0] fifos_wbw_addr_data_in = wbs_sm_data_out ;
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wire [3:0] fifos_wbw_cbe_in = wbs_sm_cbe_out ;
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wire [3:0] fifos_wbw_cbe_in = wbs_sm_cbe_out ;
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wire [3:0] fifos_wbw_control_in = wbs_sm_wbw_control_out ;
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wire [3:0] fifos_wbw_control_in = wbs_sm_wbw_control_out ;
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wire fifos_wbw_renable_in = pcim_if_wbw_renable_out ;
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wire fifos_wbw_renable_in = pcim_if_wbw_renable_out ;
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wire fifos_wbw_flush_in = 1'b0 ;
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//wire fifos_wbw_flush_in = 1'b0 ; flush for write fifo not used
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// WBR_FIFO inputs
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// WBR_FIFO inputs
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wire fifos_wbr_wenable_in = pcim_if_wbr_wenable_out ;
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wire fifos_wbr_wenable_in = pcim_if_wbr_wenable_out ;
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wire [31:0] fifos_wbr_data_in = pcim_if_wbr_data_out ;
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wire [31:0] fifos_wbr_data_in = pcim_if_wbr_data_out ;
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wire [3:0] fifos_wbr_be_in = pcim_if_wbr_be_out ;
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wire [3:0] fifos_wbr_be_in = pcim_if_wbr_be_out ;
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| Line 524... |
Line 528... |
.wbw_control_in (fifos_wbw_control_in),
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.wbw_control_in (fifos_wbw_control_in),
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.wbw_renable_in (fifos_wbw_renable_in),
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.wbw_renable_in (fifos_wbw_renable_in),
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.wbw_addr_data_out (fifos_wbw_addr_data_out),
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.wbw_addr_data_out (fifos_wbw_addr_data_out),
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.wbw_cbe_out (fifos_wbw_cbe_out),
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.wbw_cbe_out (fifos_wbw_cbe_out),
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.wbw_control_out (fifos_wbw_control_out),
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.wbw_control_out (fifos_wbw_control_out),
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.wbw_flush_in (fifos_wbw_flush_in),
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// .wbw_flush_in (fifos_wbw_flush_in), // flush for write fifo not used
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.wbw_almost_full_out (fifos_wbw_almost_full_out),
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.wbw_almost_full_out (fifos_wbw_almost_full_out),
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.wbw_full_out (fifos_wbw_full_out),
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.wbw_full_out (fifos_wbw_full_out),
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.wbw_empty_out (fifos_wbw_empty_out),
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.wbw_empty_out (fifos_wbw_empty_out),
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.wbw_transaction_ready_out (fifos_wbw_transaction_ready_out),
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.wbw_transaction_ready_out (fifos_wbw_transaction_ready_out),
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.wbr_wenable_in (fifos_wbr_wenable_in),
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.wbr_wenable_in (fifos_wbr_wenable_in),
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