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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_slave_unit.v] - Diff between revs 2 and 6

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//////////////////////////////////////////////////////////////////////
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//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
 
// New project directory structure
 
//
//
//
 
 
// Module instantiates and connects other modules lower in hierarcy
// Module instantiates and connects other modules lower in hierarcy
// Wishbone slave unit consists of modules that together form datapath
// Wishbone slave unit consists of modules that together form datapath
// between external WISHBONE masters and external PCI targets
// between external WISHBONE masters and external PCI targets
`include "constants.v"
`include "constants.v"
 
`include "timescale.v"
module WB_SLAVE_UNIT
module WB_SLAVE_UNIT
(
(
    reset_in,
    reset_in,
    wb_clock_in,
    wb_clock_in,
    pci_clock_in,
    pci_clock_in,

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