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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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//
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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| Line 144... |
Line 147... |
wbu_del_read_comp_pending_out,
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wbu_del_read_comp_pending_out,
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wbu_wbw_fifo_empty_out,
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wbu_wbw_fifo_empty_out,
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wbu_latency_tim_val_in,
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wbu_latency_tim_val_in,
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wbu_ad_load_out,
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wbu_ad_load_out,
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wbu_ad_load_on_transfer_out
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wbu_ad_load_on_transfer_out
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`ifdef PCI_BIST
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,
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// debug chain signals
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SO ,
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SI ,
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shift_DR ,
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capture_DR ,
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extest ,
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tck
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`endif
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);
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);
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input reset_in,
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input reset_in,
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wb_clock_in,
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wb_clock_in,
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pci_clock_in ;
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pci_clock_in ;
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| Line 245... |
Line 259... |
input [7:0] wbu_latency_tim_val_in ;
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input [7:0] wbu_latency_tim_val_in ;
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output wbu_ad_load_out ;
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output wbu_ad_load_out ;
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output wbu_ad_load_on_transfer_out ;
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output wbu_ad_load_on_transfer_out ;
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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BIST debug chain port signals
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-----------------------------------------------------*/
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output SO ;
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input SI ;
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input shift_DR ;
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input capture_DR ;
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input extest ;
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input tck ;
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`endif
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// pci master interface outputs
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// pci master interface outputs
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wire [31:0] pcim_if_address_out ;
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wire [31:0] pcim_if_address_out ;
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wire [3:0] pcim_if_bc_out ;
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wire [3:0] pcim_if_bc_out ;
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wire [31:0] pcim_if_data_out ;
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wire [31:0] pcim_if_data_out ;
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| Line 516... |
Line 541... |
wire [3:0] fifos_wbr_control_in = pcim_if_wbr_control_out ;
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wire [3:0] fifos_wbr_control_in = pcim_if_wbr_control_out ;
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wire fifos_wbr_renable_in = wbs_sm_wbr_renable_out ;
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wire fifos_wbr_renable_in = wbs_sm_wbr_renable_out ;
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wire fifos_wbr_flush_in = wbs_sm_wbr_flush_out || del_sync_comp_flush_out ;
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wire fifos_wbr_flush_in = wbs_sm_wbr_flush_out || del_sync_comp_flush_out ;
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// WBW_FIFO and WBR_FIFO instantiation
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// WBW_FIFO and WBR_FIFO instantiation
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WBW_WBR_FIFOS fifos(
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WBW_WBR_FIFOS fifos
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(
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.wb_clock_in (wb_clock_in),
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.wb_clock_in (wb_clock_in),
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.pci_clock_in (pci_clock_in),
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.pci_clock_in (pci_clock_in),
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.reset_in (reset_in),
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.reset_in (reset_in),
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.wbw_wenable_in (fifos_wbw_wenable_in),
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.wbw_wenable_in (fifos_wbw_wenable_in),
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.wbw_addr_data_in (fifos_wbw_addr_data_in),
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.wbw_addr_data_in (fifos_wbw_addr_data_in),
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| Line 543... |
Line 569... |
.wbr_data_out (fifos_wbr_data_out),
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.wbr_data_out (fifos_wbr_data_out),
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.wbr_be_out (fifos_wbr_be_out),
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.wbr_be_out (fifos_wbr_be_out),
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.wbr_control_out (fifos_wbr_control_out),
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.wbr_control_out (fifos_wbr_control_out),
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.wbr_flush_in (fifos_wbr_flush_in),
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.wbr_flush_in (fifos_wbr_flush_in),
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.wbr_empty_out (fifos_wbr_empty_out)
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.wbr_empty_out (fifos_wbr_empty_out)
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`ifdef PCI_BIST
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,
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.SO (SO),
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.SI (SI),
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.shift_DR (shift_DR),
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.capture_DR (capture_DR),
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.extest (extest),
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.tck (tck)
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`endif
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) ;
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) ;
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wire [31:0] amux_addr_in = ADDR_I ;
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wire [31:0] amux_addr_in = ADDR_I ;
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wire amux_sample_address_in = wbs_sm_sample_address_out ;
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wire amux_sample_address_in = wbs_sm_sample_address_out ;
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