| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/10/08 17:17:06 mihad
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// Added BIST signals for RAMs.
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//
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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// Removed all logic from asynchronous reset network
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//
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//
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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| Line 151... |
Line 154... |
wbu_ad_load_on_transfer_out
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wbu_ad_load_on_transfer_out
|
|
|
`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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|
trst ,
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SO ,
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SO ,
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SI ,
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SI ,
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shift_DR ,
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shift_DR ,
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capture_DR ,
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capture_DR ,
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extest ,
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extest ,
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| Line 263... |
Line 267... |
|
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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/*-----------------------------------------------------
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BIST debug chain port signals
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BIST debug chain port signals
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-----------------------------------------------------*/
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-----------------------------------------------------*/
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|
input trst ;
|
output SO ;
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output SO ;
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input SI ;
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input SI ;
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input shift_DR ;
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input shift_DR ;
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input capture_DR ;
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input capture_DR ;
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input extest ;
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input extest ;
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| Line 572... |
Line 577... |
.wbr_flush_in (fifos_wbr_flush_in),
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.wbr_flush_in (fifos_wbr_flush_in),
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.wbr_empty_out (fifos_wbr_empty_out)
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.wbr_empty_out (fifos_wbr_empty_out)
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
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,
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,
|
|
.trst (trst),
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.SO (SO),
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.SO (SO),
|
.SI (SI),
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.SI (SI),
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.shift_DR (shift_DR),
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.shift_DR (shift_DR),
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.capture_DR (capture_DR),
|
.capture_DR (capture_DR),
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.extest (extest),
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.extest (extest),
|
