| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/10/11 10:09:01 mihad
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// Added additional testcase and changed rst name in BIST to trst
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//
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// Revision 1.5 2002/10/08 17:17:06 mihad
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// Revision 1.5 2002/10/08 17:17:06 mihad
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// Added BIST signals for RAMs.
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// Added BIST signals for RAMs.
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//
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//
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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// Removed all logic from asynchronous reset network
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| Line 154... |
Line 157... |
wbu_ad_load_on_transfer_out
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wbu_ad_load_on_transfer_out
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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trst ,
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scanb_rst, // bist scan reset
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SO ,
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scanb_clk, // bist scan clock
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SI ,
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scanb_si, // bist scan serial in
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shift_DR ,
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scanb_so, // bist scan serial out
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capture_DR ,
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scanb_sen // bist scan shift enable
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extest ,
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tck
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`endif
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`endif
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);
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);
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input reset_in,
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input reset_in,
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wb_clock_in,
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wb_clock_in,
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| Line 267... |
Line 268... |
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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/*-----------------------------------------------------
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BIST debug chain port signals
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BIST debug chain port signals
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-----------------------------------------------------*/
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-----------------------------------------------------*/
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input trst ;
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input scanb_rst; // bist scan reset
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output SO ;
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input scanb_clk; // bist scan clock
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input SI ;
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input scanb_si; // bist scan serial in
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input shift_DR ;
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output scanb_so; // bist scan serial out
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input capture_DR ;
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input scanb_sen; // bist scan shift enable
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input extest ;
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input tck ;
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`endif
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`endif
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// pci master interface outputs
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// pci master interface outputs
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wire [31:0] pcim_if_address_out ;
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wire [31:0] pcim_if_address_out ;
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wire [3:0] pcim_if_bc_out ;
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wire [3:0] pcim_if_bc_out ;
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| Line 577... |
Line 576... |
.wbr_flush_in (fifos_wbr_flush_in),
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.wbr_flush_in (fifos_wbr_flush_in),
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.wbr_empty_out (fifos_wbr_empty_out)
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.wbr_empty_out (fifos_wbr_empty_out)
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.trst (trst),
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.scanb_rst (scanb_rst),
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.SO (SO),
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.scanb_clk (scanb_clk),
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.SI (SI),
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.scanb_si (scanb_si),
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.shift_DR (shift_DR),
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.scanb_so (scanb_so),
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.capture_DR (capture_DR),
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.scanb_sen (scanb_sen)
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.extest (extest),
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.tck (tck)
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`endif
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`endif
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) ;
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) ;
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wire [31:0] amux_addr_in = ADDR_I ;
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wire [31:0] amux_addr_in = ADDR_I ;
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wire amux_sample_address_in = wbs_sm_sample_address_out ;
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wire amux_sample_address_in = wbs_sm_sample_address_out ;
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