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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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/* FIFO_CONTROL module provides read/write address and status generation for
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/* FIFO_CONTROL module provides read/write address and status generation for
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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`include "constants.v"
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`include "pci_constants.v"
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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`ifdef FPGA
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// synopsys translate_on
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// fifo design in FPGA will be synchronous
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`ifdef SYNCHRONOUS
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`else
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`define SYNCHRONOUS
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`endif
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`endif
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module WBR_FIFO_CONTROL
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module WBR_FIFO_CONTROL
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(
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(
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rclock_in,
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rclock_in,
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wclock_in,
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wclock_in,
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wire rallow ;
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wire rallow ;
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// clear generation for FFs and registers
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// clear generation for FFs and registers
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wire clear = reset_in || flush_in ;
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wire clear = reset_in || flush_in ;
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`ifdef SYNCHRONOUS
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reg wclock_nempty_detect ;
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reg wclock_nempty_detect ;
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always@(posedge reset_in or posedge wclock_in)
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always@(posedge reset_in or posedge wclock_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
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wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
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Line 167... |
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// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
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// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
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// done for zero wait state burst
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// done for zero wait state burst
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assign raddr_out = rallow ? raddr_plus_one : raddr ;
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assign raddr_out = rallow ? raddr_plus_one : raddr ;
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// enable for this register
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wire raddr_plus_one_en = rallow ;
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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raddr_plus_one[(ADDR_LENGTH - 1):1] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0}} ;
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// initial value is 3
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raddr_plus_one[0] <= #`FF_DELAY 1'b1 ;
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raddr_plus_one <= #`FF_DELAY 3 ;
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end
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end
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else if (raddr_plus_one_en)
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else if (rallow)
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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end
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end
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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// initial value is 000......00
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// initial value is 2
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raddr <= #`FF_DELAY { ADDR_LENGTH{1'b0}} ;
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raddr <= #`FF_DELAY 2 ;
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else if (rallow)
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else if (rallow)
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raddr <= #`FF_DELAY raddr_plus_one ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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end
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end
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`else
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// asynchronous RAM storage for FIFOs - somewhat simpler control logic
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//rallow generation
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assign rallow = renable_in && ~empty ;
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assign rallow_out = rallow ;
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// read address counter - normal counter, nothing to it
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// for asynchronous implementation, there is no need for pointing to next address.
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// On clock edge that read is performed, read address will change and on the next clock edge
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// asynchronous memory will provide next data
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always@(posedge rclock_in or posedge clear)
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begin
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if (clear)
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// initial value is 000......00
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raddr <= #`FF_DELAY { ADDR_LENGTH{1'b0}} ;
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else if (rallow)
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raddr <= #`FF_DELAY raddr + 1'b1 ;
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end
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assign empty_out = empty ;
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assign raddr_out = raddr ;
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`endif
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/*-----------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------
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Read address control consists of Read address counter and Grey Address pipeline
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Read address control consists of Read address counter and Grey Address pipeline
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There are 3 Grey addresses:
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There are 3 Grey addresses:
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- rgrey_addr is Grey Code of current read address
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- rgrey_addr is Grey Code of current read address
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- rgrey_next is Grey Code of next read address
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- rgrey_next is Grey Code of next read address
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// grey code register for read address - represents current Read Address
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// grey code register for read address - represents current Read Address
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 100.......01
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// initial value is 0
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rgrey_addr[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
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rgrey_addr <= #`FF_DELAY 0 ;
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rgrey_addr[(ADDR_LENGTH - 2):1] <= #`FF_DELAY { (ADDR_LENGTH - 2){1'b0} } ;
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rgrey_addr[0] <= #`FF_DELAY 1'b1 ;
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end
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end
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else
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else
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if (rallow)
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if (rallow)
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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end
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end
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// grey code register for next read address - represents Grey Code of next read address
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// grey code register for next read address - represents Grey Code of next read address
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 100......00
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// initial value is 1
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rgrey_next[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
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rgrey_next <= #`FF_DELAY 1 ;
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rgrey_next[(ADDR_LENGTH - 2):0] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0} } ;
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end
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end
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else
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else
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if (rallow)
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if (rallow)
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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end
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end
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// grey code register for write address
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// grey code register for write address
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 100.....001
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// initial value is 0
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wgrey_addr[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
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wgrey_addr <= #`FF_DELAY 0 ;
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wgrey_addr[(ADDR_LENGTH - 2):1] <= #`FF_DELAY { (ADDR_LENGTH - 2){1'b0} } ;
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wgrey_addr[0] <= #`FF_DELAY 1'b1 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow)
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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end
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end
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// grey code register for next write address
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// grey code register for next write address
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 100......00
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// initial value is 1
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wgrey_next[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
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wgrey_next <= #`FF_DELAY 1 ;
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wgrey_next[(ADDR_LENGTH - 2):0] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0} } ;
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end
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end
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else
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else
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if (wallow)
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if (wallow)
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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end
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end
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// write address counter - nothing special
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// write address counter - nothing special except initial value
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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// initial value 00.........00
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// initial value is 2
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waddr <= #`FF_DELAY { (ADDR_LENGTH){1'b0} } ;
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waddr <= #`FF_DELAY 2 ;
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else
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else
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if (wallow)
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if (wallow)
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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end
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end
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