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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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Line 132... |
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// read allow wire
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// read allow wire
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wire rallow ;
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wire rallow ;
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// clear generation for FFs and registers
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// clear generation for FFs and registers
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wire clear = reset_in || flush_in ;
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wire clear = reset_in /*|| flush_in*/ ; // flush changed to synchronous operation
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reg wclock_nempty_detect ;
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reg wclock_nempty_detect ;
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always@(posedge reset_in or posedge wclock_in)
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always@(posedge reset_in or posedge wclock_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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Line 173... |
assign raddr_out = rallow ? raddr_plus_one : raddr ;
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assign raddr_out = rallow ? raddr_plus_one : raddr ;
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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// initial value is 3
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// initial value is 3
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raddr_plus_one <= #`FF_DELAY 3 ;
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raddr_plus_one <= #`FF_DELAY 3 ;
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end
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else if (flush_in)
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raddr_plus_one <= #`FF_DELAY waddr + 1'b1 ; // when read fifo is flushed, values from write side are copied to read side
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else if (rallow)
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else if (rallow)
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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end
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end
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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// initial value is 2
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// initial value is 2
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raddr <= #`FF_DELAY 2 ;
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raddr <= #`FF_DELAY 2 ;
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else if (flush_in)
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raddr <= #`FF_DELAY waddr ; // when flushed, copy value from write side
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else if (rallow)
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else if (rallow)
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raddr <= #`FF_DELAY raddr_plus_one ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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end
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end
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/*-----------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------
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Line 204... |
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// grey code register for read address - represents current Read Address
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// grey code register for read address - represents current Read Address
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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// initial value is 0
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// initial value is 0
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rgrey_addr <= #`FF_DELAY 0 ;
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rgrey_addr <= #`FF_DELAY 0 ;
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end
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else if (flush_in)
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else
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rgrey_addr <= #`FF_DELAY wgrey_addr ; // when flushed, copy value from write side
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if (rallow)
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else if (rallow)
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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end
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end
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// grey code register for next read address - represents Grey Code of next read address
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// grey code register for next read address - represents Grey Code of next read address
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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// initial value is 1
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// initial value is 1
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rgrey_next <= #`FF_DELAY 1 ;
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rgrey_next <= #`FF_DELAY 1 ;
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end
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else if (flush_in)
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else
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rgrey_next <= #`FF_DELAY wgrey_next ;
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if (rallow)
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else if (rallow)
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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end
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end
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/*--------------------------------------------------------------------------------------------
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/*--------------------------------------------------------------------------------------------
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Write address control consists of write address counter and two Grey Code Registers:
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Write address control consists of write address counter and two Grey Code Registers:
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Line 280... |
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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empty <= #`FF_DELAY 1'b1 ;
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empty <= #`FF_DELAY 1'b1 ;
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else if (flush_in)
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empty <= #1 1'b1 ; // when flushed, set empty to active
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else
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else
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empty <= #`FF_DELAY reg_empty ;
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empty <= #`FF_DELAY reg_empty ;
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end
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end
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endmodule
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endmodule
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