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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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//
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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// next read gray address calculation - bitwise xor between address and shifted address
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// next read gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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// FF for registered empty flag
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// FF for registered empty flag
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reg empty ;
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wire empty ;
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// write allow wire
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// write allow wire
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wire wallow = wenable_in ;
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wire wallow = wenable_in ;
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// write allow output assignment
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// write allow output assignment
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else
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else
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wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
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wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
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end
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end
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// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
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// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
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reg stretched_empty ;
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wire stretched_empty ;
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always@(posedge rclock_in or posedge clear)
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begin
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wire stretched_empty_flop_i = empty && !wclock_nempty_detect ;
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if(clear)
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stretched_empty <= #`FF_DELAY 1'b1 ;
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meta_flop #(1) i_meta_flop_stretched_empty
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else
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(
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stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
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.rst_i (clear),
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end
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.clk_i (rclock_in),
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.ld_i (1'b0),
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.ld_val_i (1'b0),
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.en_i (1'b1),
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.d_i (stretched_empty_flop_i),
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.meta_q_o (stretched_empty)
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) ;
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// empty output is actual empty + 1 read clock cycle ( stretched empty )
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// empty output is actual empty + 1 read clock cycle ( stretched empty )
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assign empty_out = empty || stretched_empty ;
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assign empty_out = empty || stretched_empty ;
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//rallow generation
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//rallow generation
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assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
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assign rallow = renable_in && !empty && !stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
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// rallow output assignment
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// rallow output assignment
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assign rallow_out = renable_in ;
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assign rallow_out = renable_in ;
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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the next read clock.
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the next read clock.
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--------------------------------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------------------------------*/
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// combinatorial input for registered emty FlipFlop
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// combinatorial input for registered emty FlipFlop
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wire reg_empty = (rallow && (rgrey_next == wgrey_addr)) || (rgrey_addr == wgrey_addr) ;
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wire reg_empty = (rallow && (rgrey_next == wgrey_addr)) || (rgrey_addr == wgrey_addr) ;
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always@(posedge rclock_in or posedge clear)
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meta_flop #(1) i_meta_flop_empty
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begin
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(
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if (clear)
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.rst_i (clear),
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empty <= #`FF_DELAY 1'b1 ;
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.clk_i (rclock_in),
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else if (flush_in)
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.ld_i (flush_in),
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empty <= #1 1'b1 ; // when flushed, set empty to active
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.ld_val_i (1'b1),
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else
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.en_i (1'b1),
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empty <= #`FF_DELAY reg_empty ;
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.d_i (reg_empty),
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end
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.meta_q_o (empty)
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) ;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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