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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wbw_fifo_control.v] - Diff between revs 21 and 58

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Rev 21 Rev 58
Line 40... Line 40...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2002/02/01 15:25:14  mihad
 
// Repaired a few bugs, updated specification, added test bench files and design document
 
//
// Revision 1.2  2001/10/05 08:14:30  mihad
// Revision 1.2  2001/10/05 08:14:30  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
// Updated all files with inclusion of timescale file for simulation purposes.
//
//
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
// New project directory structure
// New project directory structure
Line 62... Line 65...
    rclock_in,
    rclock_in,
    wclock_in,
    wclock_in,
    renable_in,
    renable_in,
    wenable_in,
    wenable_in,
    reset_in,
    reset_in,
    flush_in,
//    flush_in, // not used
    almost_full_out,
    almost_full_out,
    full_out,
    full_out,
    empty_out,
    empty_out,
    waddr_out,
    waddr_out,
    raddr_out,
    raddr_out,
Line 85... Line 88...
 
 
// reset input
// reset input
input  reset_in;
input  reset_in;
 
 
// flush input
// flush input
input flush_in ;
// input flush_in ; // not used
 
 
// almost full and empy status outputs
// almost full and empy status outputs
output almost_full_out ;
output almost_full_out ;
 
 
// full and empty status outputs
// full and empty status outputs
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// almost full output assignment
// almost full output assignment
assign almost_full_out  = almost_full && ~full ;
assign almost_full_out  = almost_full && ~full ;
 
 
// clear generation for FFs and registers
// clear generation for FFs and registers
wire clear = reset_in || flush_in ;
wire clear = reset_in /*|| flush_in*/ ;     // flush not used
 
 
reg wclock_nempty_detect ;
reg wclock_nempty_detect ;
always@(posedge reset_in or posedge wclock_in)
always@(posedge clear or posedge wclock_in)
begin
begin
    if (reset_in)
    if (clear)
        wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
        wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
    else
    else
        wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
        wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
end
end
 
 

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