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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/09/30 16:03:04 mihad
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// Added meta flop module for easier meta stable FF identification during synthesis
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//
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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// Removed all logic from asynchronous reset network
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//
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//
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// Revision 1.3 2002/02/01 15:25:14 mihad
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// Revision 1.3 2002/02/01 15:25:14 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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Line 200... |
Line 203... |
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is important - raddr initial value is 4, so this one is 5
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raddr_plus_one <= #`FF_DELAY 5 ;
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raddr_plus_one <= #`FF_DELAY 5 ;
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raddr <= #`FF_DELAY 4 ;
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end
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end
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else if (rallow)
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else if (rallow)
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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end
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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// initial value is 4
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raddr <= #`FF_DELAY 4 ;
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else if (rallow)
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raddr <= #`FF_DELAY raddr_plus_one ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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end
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end
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end
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/*-----------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------
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Read address control consists of Read address counter and Grey Address pipeline
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Read address control consists of Read address counter and Grey Address pipeline
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There are 4 Grey addresses:
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There are 4 Grey addresses:
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- rgrey_minus2 is Grey Code of address two before current address
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- rgrey_minus2 is Grey Code of address two before current address
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- rgrey_minus1 is Grey Code of address one before current address
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- rgrey_minus1 is Grey Code of address one before current address
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- rgrey_addr is Grey Code of current read address
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- rgrey_addr is Grey Code of current read address
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- rgrey_next is Grey Code of next read address
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- rgrey_next is Grey Code of next read address
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--------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------*/
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// grey coded address pipeline for status generation in read clock domain
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// grey code register for two before read address
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 0
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// initial value is 0
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rgrey_minus2 <= #`FF_DELAY 0 ;
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rgrey_minus2 <= #`FF_DELAY 0 ;
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end
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else
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if (rallow)
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rgrey_minus2 <= #`FF_DELAY rgrey_minus1 ;
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end
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// grey code register for one before read address
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always@(posedge rclock_in or posedge clear)
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begin
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if (clear)
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begin
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// initial value is 1
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rgrey_minus1 <= #`FF_DELAY 1 ;
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rgrey_minus1 <= #`FF_DELAY 1 ;
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end
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else
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if (rallow)
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rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
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end
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// grey code register for read address - represents current Read Address
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always@(posedge rclock_in or posedge clear)
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begin
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if (clear)
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begin
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// initial value is 3 = ...00011
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rgrey_addr <= #`FF_DELAY 3 ;
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rgrey_addr <= #`FF_DELAY 3 ;
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end
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else
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if (rallow)
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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end
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// grey code register for next read address - represents Grey Code of next read address
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always@(posedge rclock_in or posedge clear)
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begin
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if (clear)
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begin
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// initial value is 2 = ...00010
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rgrey_next <= #`FF_DELAY 2 ;
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rgrey_next <= #`FF_DELAY 2 ;
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end
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end
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else
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else
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if (rallow)
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if (rallow)
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begin
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rgrey_minus2 <= #`FF_DELAY rgrey_minus1 ;
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rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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end
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end
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end
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/*--------------------------------------------------------------------------------------------
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/*--------------------------------------------------------------------------------------------
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Write address control consists of write address counter and two Grey Code Registers:
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Write address control consists of write address counter and two Grey Code Registers:
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- wgrey_addr represents current Grey Coded write address
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- wgrey_addr represents current Grey Coded write address
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- wgrey_next represents Grey Coded next write address
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- wgrey_next represents Grey Coded next write address
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----------------------------------------------------------------------------------------------*/
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----------------------------------------------------------------------------------------------*/
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// grey code register for write address
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// grey coded address pipeline for status generation in write clock domain
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
|
if (clear)
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begin
|
begin
|
// initial value is 3 = ....011
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|
wgrey_addr <= #`FF_DELAY 3 ;
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wgrey_addr <= #`FF_DELAY 3 ;
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end
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else
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if (wallow)
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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end
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// grey code register for next write address
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always@(posedge wclock_in or posedge clear)
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begin
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if (clear)
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begin
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// initial value is 2 = ...010
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wgrey_next <= #`FF_DELAY 2 ;
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wgrey_next <= #`FF_DELAY 2 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow)
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begin
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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end
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end
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|
end
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|
|
// write address counter - nothing special - initial value is important though
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// write address counter - nothing special - initial value is important though
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|