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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wbw_wbr_fifos.v] - Diff between revs 7 and 21

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.2  2001/10/05 08:20:12  mihad
 
// Updated all files with inclusion of timescale file for simulation purposes.
 
//
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
// New project directory structure
// New project directory structure
//
//
//
//
 
 
`include "constants.v"
`include "pci_constants.v"
 
 
 
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
 
// synopsys translate_on
 
 
module WBW_WBR_FIFOS(
module WBW_WBR_FIFOS(
                        wb_clock_in,
                        wb_clock_in,
                        pci_clock_in,
                        pci_clock_in,
                        reset_in,
                        reset_in,
Line 226... Line 232...
-----------------------------------------------------------------------------------------------------------*/
-----------------------------------------------------------------------------------------------------------*/
reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;
reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;
 
 
/*-----------------------------------------------------------------------------------------------------------
/*-----------------------------------------------------------------------------------------------------------
FlipFlops for indicating if complete delayed read completion is present in the FIFO
 
-----------------------------------------------------------------------------------------------------------*/
 
/*reg wbr_inTransactionCount ;
 
reg wbr_outTransactionCount ;*/
 
/*-----------------------------------------------------------------------------------------------------------
 
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
it means that there was one complete transaction taken out of FIFO.
it means that there was one complete transaction taken out of FIFO.
-----------------------------------------------------------------------------------------------------------*/
-----------------------------------------------------------------------------------------------------------*/
wire wbw_last_in  = wbw_control_in[`LAST_CTRL_BIT]  ;
wire wbw_last_in  = wbw_control_in[`LAST_CTRL_BIT]  ;
wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;
wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;
 
 
/*wire wbr_last_in  = wbr_wallow && wbr_control_in[`LAST_CTRL_BIT] ;
 
wire wbr_last_out = wbr_rallow && wbr_control_out[`LAST_CTRL_BIT] ;*/
 
 
 
wire wbw_empty ;
wire wbw_empty ;
wire wbr_empty ;
wire wbr_empty ;
 
 
assign wbw_empty_out = wbw_empty ;
assign wbw_empty_out = wbw_empty ;
assign wbr_empty_out = wbr_empty ;
assign wbr_empty_out = wbr_empty ;
 
 
// clear wires for fifos
// clear wires for fifos
wire wbw_clear = reset_in || wbw_flush_in ; // WBW_FIFO clear
wire wbw_clear = reset_in || wbw_flush_in ; // WBW_FIFO clear
wire wbr_clear = reset_in || wbr_flush_in ; // WBR_FIFO clear
wire wbr_clear = reset_in || wbr_flush_in ; // WBR_FIFO clear
 
 
`ifdef FPGA
 
/*-----------------------------------------------------------------------------------------------------------
/*-----------------------------------------------------------------------------------------------------------
this code is included only for FPGA core usage - somewhat different logic because of sharing
Definitions of wires for connecting RAM instances
one block selectRAM+ between two FIFOs
 
-----------------------------------------------------------------------------------------------------------*/
-----------------------------------------------------------------------------------------------------------*/
    `ifdef BIG
wire [39:0] dpram_portA_output ;
 
wire [39:0] dpram_portB_output ;
 
 
 
wire [39:0] dpram_portA_input = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
 
wire [39:0] dpram_portB_input = {wbr_control_in, wbr_be_in, wbr_data_in} ;
 
 
        /*-----------------------------------------------------------------------------------------------------------
        /*-----------------------------------------------------------------------------------------------------------
        Big FPGAs
Fifo output assignments - each ram port provides data for different fifo
        WBW_FIFO and WBR_FIFO address prefixes - used for extending read and write addresses because of varible
 
        FIFO depth and fixed SelectRAM+ size. Addresses are zero paded on the left to form long enough address
 
        -----------------------------------------------------------------------------------------------------------*/
        -----------------------------------------------------------------------------------------------------------*/
        wire [(7 - WBW_ADDR_LENGTH):0] wbw_addr_prefix = {( 8 - WBW_ADDR_LENGTH){1'b0}} ;
assign wbw_control_out = dpram_portB_output[39:36] ;
        wire [(7 - WBR_ADDR_LENGTH):0] wbr_addr_prefix = {( 8 - WBR_ADDR_LENGTH){1'b0}} ;
assign wbr_control_out = dpram_portA_output[39:36] ;
 
 
        // compose addresses
assign wbw_cbe_out     = dpram_portB_output[35:32] ;
        wire [7:0] wbw_whole_waddr = {wbw_addr_prefix, wbw_waddr} ;
assign wbr_be_out      = dpram_portA_output[35:32] ;
        wire [7:0] wbw_whole_raddr = {wbw_addr_prefix, wbw_raddr} ;
 
 
 
        wire [7:0] wbr_whole_waddr = {wbr_addr_prefix, wbr_waddr} ;
assign wbw_addr_data_out = dpram_portB_output[31:0] ;
        wire [7:0] wbr_whole_raddr = {wbr_addr_prefix, wbr_raddr} ;
assign wbr_data_out      = dpram_portA_output[31:0] ;
 
 
 
`ifdef WB_RAM_DONT_SHARE
 
 
        /*-----------------------------------------------------------------------------------------------------------
        /*-----------------------------------------------------------------------------------------------------------
        Only 8 bits out of 16 are used in ram3 and ram6 - wires for referencing them
    Piece of code in this ifdef section is used in applications which can provide enough RAM instances to
 
    accomodate four fifos - each occupying its own instance of ram. Ports are connected in such a way,
 
    that instances of RAMs can be changed from two port to dual port ( async read/write port ). In that case,
 
    write port is always port a and read port is port b.
        -----------------------------------------------------------------------------------------------------------*/
        -----------------------------------------------------------------------------------------------------------*/
        wire [15:0] dpram3_portB_output ;
 
        wire [15:0] dpram6_portA_output ;
 
 
 
        /*-----------------------------------------------------------------------------------------------------------
        /*-----------------------------------------------------------------------------------------------------------
        Control out assignements from ram3 output
    Pad redundant address lines with zeros. This may seem stupid, but it comes in perfect for FPGA impl.
        -----------------------------------------------------------------------------------------------------------*/
        -----------------------------------------------------------------------------------------------------------*/
        assign wbw_control_out = dpram3_portB_output[15:12] ;
    /*
        assign wbr_control_out = dpram6_portA_output[15:12] ;
    wire [(`WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
 
    wire [(`WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b0}} ;
 
    */
 
 
        assign wbw_cbe_out = dpram3_portB_output[3:0] ;
    // compose complete port addresses
        assign wbr_be_out  = dpram6_portA_output[3:0] ;
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_waddr = wbw_waddr ;
 
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_raddr = wbw_raddr ;
 
 
 
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_waddr = wbr_waddr ;
 
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;
 
 
        wire wbw_read_enable = 1'b1 ;
        wire wbw_read_enable = 1'b1 ;
        wire wbr_read_enable = 1'b1 ;
        wire wbr_read_enable = 1'b1 ;
 
 
        // Block SelectRAM+ cells instantiation
    // instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
        RAMB4_S16_S16 dpram16_1 (.ADDRA(wbw_whole_waddr), .DIA(wbw_addr_data_in[15:0]),
    WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
                                 .ENA(vcc), .RSTA(reset_in),
    (
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow),
        // Generic synchronous two-port RAM interface
                                 .DOA(),
        .clk_a(wb_clock_in),
                                 .ADDRB(wbw_whole_raddr), .DIB(16'h0000),
        .rst_a(reset_in),
                                 .ENB(wbw_read_enable), .RSTB(reset_in),
        .ce_a(1'b1),
                                 .CLKB(pci_clock_in), .WEB(gnd),
        .we_a(wbw_wallow),
                                 .DOB(wbw_addr_data_out[15:0])) ;
        .oe_a(1'b1),
 
        .addr_a(wbw_whole_waddr),
        RAMB4_S16_S16 dpram16_2 (.ADDRA(wbw_whole_waddr), .DIA(wbw_addr_data_in[31:16]),
        .di_a(dpram_portA_input),
                                 .ENA(vcc), .RSTA(reset_in),
        .do_a(),
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow),
 
                                 .DOA(),
        .clk_b(pci_clock_in),
                                 .ADDRB(wbw_whole_raddr), .DIB(16'h0000),
        .rst_b(reset_in),
                                 .ENB(wbw_read_enable), .RSTB(reset_in),
        .ce_b(wbw_read_enable),
                                 .CLKB(pci_clock_in), .WEB(gnd),
        .we_b(1'b0),
                                 .DOB(wbw_addr_data_out[31:16])) ;
        .oe_b(1'b1),
 
        .addr_b(wbw_whole_raddr),
        RAMB4_S16_S16 dpram16_3 (.ADDRA(wbw_whole_waddr), .DIA({wbw_control_in, 8'h00, wbw_cbe_in}),
        .di_b(40'h00_0000_0000),
                                 .ENA(vcc), .RSTA(reset_in),
        .do_b(dpram_portB_output)
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow),
    );
                                 .DOA(),
 
                                 .ADDRB(wbw_whole_raddr), .DIB(16'h0000),
 
                                 .ENB(wbw_read_enable), .RSTB(reset_in),
 
                                 .CLKB(pci_clock_in), .WEB(gnd),
 
                                 .DOB(dpram3_portB_output)) ;
 
 
 
        RAMB4_S16_S16 dpram16_4 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
 
                                 .ENA(1'b1), .RSTA(reset_in),
 
                                 .CLKA(wb_clock_in), .WEA(gnd),
 
                                 .DOA(wbr_data_out[15:0]),
 
                                 .ADDRB(wbr_whole_waddr), .DIB(wbr_data_in[15:0]),
 
                                 .ENB(wbr_read_enable), .RSTB(reset_in),
 
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow),
 
                                 .DOB()) ;
 
 
 
        RAMB4_S16_S16 dpram16_5 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
 
                                 .ENA(1'b1), .RSTA(reset_in),
 
                                 .CLKA(wb_clock_in), .WEA(gnd),
 
                                 .DOA(wbr_data_out[31:16]),
 
                                 .ADDRB(wbr_whole_waddr), .DIB(wbr_data_in[31:16]),
 
                                 .ENB(wbr_read_enable), .RSTB(reset_in),
 
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow),
 
                                 .DOB()) ;
 
 
 
        RAMB4_S16_S16 dpram16_6 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
 
                                 .ENA(1'b1), .RSTA(reset_in),
 
                                 .CLKA(wb_clock_in), .WEA(gnd),
 
                                 .DOA(dpram6_portA_output),
 
                                 .ADDRB(wbr_whole_waddr), .DIB({wbr_control_in, 8'h00, wbr_be_in}),
 
                                 .ENB(wbr_read_enable), .RSTB(reset_in),
 
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow),
 
                                 .DOB()) ;
 
 
 
    `else // SMALL FPGAs
 
 
 
        /*-----------------------------------------------------------------------------------------------------------
 
        Small FPGAs
 
        WBW_FIFO and WBR_FIFO address prefixes - used for extending read and write addresses because of varible
 
        FIFO depth and fixed SelectRAM+ size. Addresses are always paded, because of RAM sharing between FIFOs
 
        WBW addresses are zero padded on the left, WBR addresses are padded
 
        with ones on the left
 
        -----------------------------------------------------------------------------------------------------------*/
 
        wire [(7 - WBW_ADDR_LENGTH):0] wbw_addr_prefix = {( 8 - WBW_ADDR_LENGTH){1'b0}} ;
 
        wire [(7 - WBR_ADDR_LENGTH):0] wbr_addr_prefix = {( 8 - WBR_ADDR_LENGTH){1'b1}} ;
 
 
 
        /*-----------------------------------------------------------------------------------------------------------
 
        Only 8 bits out of 16 are used in ram3 - wires for referencing them
 
        -----------------------------------------------------------------------------------------------------------*/
 
        wire [15:0] dpram3_portA_output ;
 
        wire [15:0] dpram3_portB_output ;
 
 
 
        /*-----------------------------------------------------------------------------------------------------------
 
        Control out assignements from ram3 output
 
        -----------------------------------------------------------------------------------------------------------*/
 
        assign wbw_control_out = dpram3_portB_output[15:12] ;
 
        assign wbr_control_out = dpram3_portA_output[15:12] ;
 
 
 
        assign wbw_cbe_out = dpram3_portB_output[3:0] ;
 
        assign wbr_be_out  = dpram3_portA_output[3:0] ;
 
 
 
        /*-----------------------------------------------------------------------------------------------------------
 
        Port A address generation for block SelectRam+ in SpartanII or Virtex
 
        Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo. Address is multiplexed
 
        between two values.
 
        Address multiplexing:
 
        wbw_wenable == 1 => ADDRA = wbw_waddr (write pointer of WBW_FIFO)
 
        else                ADDRA = wbr_raddr (read pointer of WBR_FIFO)
 
        -----------------------------------------------------------------------------------------------------------*/
 
        wire [7:0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;
 
 
 
        /*-----------------------------------------------------------------------------------------------------------
 
        Port B address generation for block SelectRam+ in SpartanII or Virtex
 
        Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo. Address is multiplexed
 
        between two values.
 
        Address multiplexing:
 
        wbr_wenable == 1 => ADDRB = wbr_waddr (write pointer of WBR_FIFO)
 
        else                ADDRB = wbw_raddr (read pointer of WBW_FIFO)
 
        -----------------------------------------------------------------------------------------------------------*/
 
        wire [7:0] portB_addr  = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;
 
 
 
        wire portA_enable      = 1'b1 ;
    WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
 
    (
 
        // Generic synchronous two-port RAM interface
 
        .clk_a(pci_clock_in),
 
        .rst_a(reset_in),
 
        .ce_a(1'b1),
 
        .we_a(wbr_wallow),
 
        .oe_a(1'b1),
 
        .addr_a(wbr_whole_waddr),
 
        .di_a(dpram_portB_input),
 
        .do_a(),
 
 
 
        .clk_b(wb_clock_in),
 
        .rst_b(reset_in),
 
        .ce_b(wbr_read_enable),
 
        .we_b(1'b0),
 
        .oe_b(1'b1),
 
        .addr_b(wbr_whole_raddr),
 
        .di_b(40'h00_0000_0000),
 
        .do_b(dpram_portA_output)
 
    );
 
 
        wire portB_enable      = 1'b1 ;
`else // RAM blocks sharing between two fifos
 
 
        // Block SelectRAM+ cells instantiation
    /*-----------------------------------------------------------------------------------------------------------
        RAMB4_S16_S16 dpram16_1 (.ADDRA(portA_addr), .DIA(wbw_addr_data_in[15:0]),
    Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
                                 .ENA(portA_enable), .RSTA(reset_in),
    case one RAM instance is used for both - WISHBONE read and WISHBONE write fifo.
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow),
    -----------------------------------------------------------------------------------------------------------*/
                                 .DOA(wbr_data_out[15:0]),
    /*-----------------------------------------------------------------------------------------------------------
                                 .ADDRB(portB_addr), .DIB(wbr_data_in[15:0]),
    Address prefix definition - since both FIFOs reside in same RAM instance, storage is separated by MSB
                                 .ENB(portB_enable), .RSTB(reset_in),
    addresses. WISHBONE write fifo addresses are padded with zeros on the MSB side ( at least one address line
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow),
    must be used for this ), WISHBONE read fifo addresses are padded with ones on the right ( at least one ).
                                 .DOB(wbw_addr_data_out[15:0])) ;
    -----------------------------------------------------------------------------------------------------------*/
 
    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
        RAMB4_S16_S16 dpram16_2 (.ADDRA(portA_addr), .DIA(wbw_addr_data_in[31:16]),
    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b1}} ;
                                 .ENA(portA_enable), .RSTA(reset_in),
 
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow),
 
                                 .DOA(wbr_data_out[31:16]),
 
                                 .ADDRB(portB_addr), .DIB(wbr_data_in[31:16]),
 
                                 .ENB(portB_enable), .RSTB(reset_in),
 
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow),
 
                                 .DOB(wbw_addr_data_out[31:16])) ;
 
 
 
        RAMB4_S16_S16 dpram16_3 (.ADDRA(portA_addr), .DIA({wbw_control_in, 8'h00, wbw_cbe_in}),
 
                                 .ENA(portA_enable), .RSTA(reset_in),
 
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow),
 
                                 .DOA(dpram3_portA_output),
 
                                 .ADDRB(portB_addr), .DIB({wbr_control_in, 8'h00, wbr_be_in}),
 
                                 .ENB(portB_enable), .RSTB(reset_in),
 
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow),
 
                                 .DOB(dpram3_portB_output)) ;
 
    `endif
 
 
 
 
    /*-----------------------------------------------------------------------------------------------------------
 
    Port A address generation for RAM instance. RAM instance must be full two port RAM - read and write capability
 
    on both sides.
 
    Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo.
 
    Address is multiplexed so operation can be switched between fifos. Default is a read on port.
 
    -----------------------------------------------------------------------------------------------------------*/
 
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;
 
 
 
    /*-----------------------------------------------------------------------------------------------------------
 
    Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo.
 
    Address is multiplexed so operation can be switched between fifos. Default is a read on port.
 
    -----------------------------------------------------------------------------------------------------------*/
 
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr  = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;
 
 
 
    wire portA_enable      = 1'b1 ;
 
 
 
    wire portB_enable      = 1'b1 ;
 
 
`else
    // instantiate RAM for these two fifos
    wire [39:0] wbw_ram_data_out ;
    WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage
    wire [39:0] wbw_ram_data_in = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
    (
    wire [39:0] wbr_ram_data_in = {wbr_control_in, wbr_be_in, wbr_data_in} ;
        // Generic synchronous two-port RAM interface
    wire [39:0] wbr_ram_data_out ;
        .clk_a(wb_clock_in),
    assign wbw_control_out   = wbw_ram_data_out[39:36] ;
        .rst_a(reset_in),
    assign wbw_cbe_out       = wbw_ram_data_out[35:32] ;
        .ce_a(portA_enable),
    assign wbw_addr_data_out = wbw_ram_data_out [31:0] ;
        .we_a(wbw_wallow),
 
        .oe_a(1'b1),
    assign wbr_control_out   = wbr_ram_data_out[39:36] ;
        .addr_a(portA_addr),
    assign wbr_be_out        = wbr_ram_data_out[35:32] ;
        .di_a(dpram_portA_input),
    assign wbr_data_out      = wbr_ram_data_out [31:0] ;
        .do_a(dpram_portA_output),
 
        .clk_b(pci_clock_in),
    `ifdef SYNCHRONOUS
        .rst_b(reset_in),
    /*-----------------------------------------------------------------------------------------------------------
        .ce_b(portB_enable),
    ASIC memory primitives will be added here in the near future - currently there is only some generic,
        .we_b(wbr_wallow),
    behavioral dual port ram here
        .oe_b(1'b1),
    -----------------------------------------------------------------------------------------------------------*/
        .addr_b(portB_addr),
    DP_SRAM #(WBW_ADDR_LENGTH, WBW_DEPTH) wbw_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .rclock_in(pci_clock_in), .data_in(wbw_ram_data_in),
        .di_b(dpram_portB_input),
                    .raddr_in(wbw_raddr), .waddr_in(wbw_waddr), .data_out(wbw_ram_data_out), .renable_in(1'b1), .wenable_in(wbw_wallow));
        .do_b(dpram_portB_output)
 
    );
    DP_SRAM #(WBR_ADDR_LENGTH, WBR_DEPTH) wbr_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .rclock_in(wb_clock_in), .data_in(wbr_ram_data_in),
 
                    .raddr_in(wbr_raddr), .waddr_in(wbr_waddr), .data_out(wbr_ram_data_out), .renable_in(1'b1), .wenable_in(wbr_wallow));
 
 
 
    `else //ASYNCHRONOUS RAM
 
        DP_ASYNC_RAM #(WBW_ADDR_LENGTH, WBW_DEPTH) wbw_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .data_in(wbw_ram_data_in),
 
                    .raddr_in(wbw_raddr), .waddr_in(wbw_waddr), .data_out(wbw_ram_data_out), .wenable_in(wbw_wallow));
 
 
 
        DP_ASYNC_RAM #(WBR_ADDR_LENGTH, WBR_DEPTH) wbr_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .data_in(wbr_ram_data_in),
 
                    .raddr_in(wbr_raddr), .waddr_in(wbr_waddr), .data_out(wbr_ram_data_out), .wenable_in(wbr_wallow));
 
    `endif
 
`endif
`endif
 
 
/*-----------------------------------------------------------------------------------------------------------
/*-----------------------------------------------------------------------------------------------------------
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
-----------------------------------------------------------------------------------------------------------*/
-----------------------------------------------------------------------------------------------------------*/
WBW_FIFO_CONTROL #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
WBW_FIFO_CONTROL #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
              (.rclock_in(pci_clock_in), .wclock_in(wb_clock_in), .renable_in(wbw_renable_in),
(
               .wenable_in(wbw_wenable_in), .reset_in(reset_in), .flush_in(wbw_flush_in),
    .rclock_in(pci_clock_in),
               .almost_full_out(wbw_almost_full_out), .full_out(wbw_full_out),
    .wclock_in(wb_clock_in),
 
    .renable_in(wbw_renable_in),
 
    .wenable_in(wbw_wenable_in),
 
    .reset_in(reset_in),
 
    .flush_in(wbw_flush_in),
 
    .almost_full_out(wbw_almost_full_out),
 
    .full_out(wbw_full_out),
               .empty_out(wbw_empty),
               .empty_out(wbw_empty),
               .waddr_out(wbw_waddr), .raddr_out(wbw_raddr),
    .waddr_out(wbw_waddr),
               .rallow_out(wbw_rallow), .wallow_out(wbw_wallow));
    .raddr_out(wbw_raddr),
 
    .rallow_out(wbw_rallow),
 
    .wallow_out(wbw_wallow)
 
);
 
 
WBR_FIFO_CONTROL #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
WBR_FIFO_CONTROL #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
                  (.rclock_in(wb_clock_in), .wclock_in(pci_clock_in), .renable_in(wbr_renable_in),
(   .rclock_in(wb_clock_in),
                   .wenable_in(wbr_wenable_in), .reset_in(reset_in), .flush_in(wbr_flush_in),
    .wclock_in(pci_clock_in),
 
    .renable_in(wbr_renable_in),
 
    .wenable_in(wbr_wenable_in),
 
    .reset_in(reset_in),
 
    .flush_in(wbr_flush_in),
                   .empty_out(wbr_empty),
                   .empty_out(wbr_empty),
                   .waddr_out(wbr_waddr), .raddr_out(wbr_raddr),
    .waddr_out(wbr_waddr),
                   .rallow_out(wbr_rallow), .wallow_out(wbr_wallow));
    .raddr_out(wbr_raddr),
 
    .rallow_out(wbr_rallow),
 
    .wallow_out(wbr_wallow)
 
);
 
 
 
 
// in and out transaction counters and grey codes
// in and out transaction counters and grey codes
reg  [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
reg  [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
reg  [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
reg  [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
 
 
 
// input transaction counter increment - when last data of transaction is written to fifo
wire in_count_en  = wbw_wallow && wbw_last_in ;
wire in_count_en  = wbw_wallow && wbw_last_in ;
 
 
 
// output transaction counter increment - when last data is on top of fifo and read from it
wire out_count_en = wbw_renable_in && wbw_last_out ;
wire out_count_en = wbw_renable_in && wbw_last_out ;
 
 
 
// register holding grey coded count of incoming transactions
always@(posedge wb_clock_in or posedge wbw_clear)
always@(posedge wb_clock_in or posedge wbw_clear)
begin
begin
    if (wbw_clear)
    if (wbw_clear)
    begin
    begin
        inGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
        inGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
Line 502... Line 458...
    else
    else
    if (in_count_en)
    if (in_count_en)
        inGreyCount <= #`FF_DELAY inNextGreyCount ;
        inGreyCount <= #`FF_DELAY inNextGreyCount ;
end
end
 
 
 
// register holding grey coded count of outgoing transactions
always@(posedge pci_clock_in or posedge wbw_clear)
always@(posedge pci_clock_in or posedge wbw_clear)
begin
begin
    if (wbw_clear)
    if (wbw_clear)
    begin
    begin
        outGreyCount[(WBW_ADDR_LENGTH-2)]   <= #`FF_DELAY 1'b1 ;
        outGreyCount[(WBW_ADDR_LENGTH-2)]   <= #`FF_DELAY 1'b1 ;
Line 514... Line 471...
    else
    else
    if (out_count_en)
    if (out_count_en)
        outGreyCount <= #`FF_DELAY outNextGreyCount ;
        outGreyCount <= #`FF_DELAY outNextGreyCount ;
end
end
 
 
 
// incoming transactions counter
always@(posedge wb_clock_in or posedge wbw_clear)
always@(posedge wb_clock_in or posedge wbw_clear)
begin
begin
    if (wbw_clear)
    if (wbw_clear)
        wbw_inTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
        wbw_inTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
    else
    else
    if (in_count_en)
    if (in_count_en)
        wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
        wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
end
end
 
 
 
// outgoing transactions counter
always@(posedge pci_clock_in or posedge wbw_clear)
always@(posedge pci_clock_in or posedge wbw_clear)
begin
begin
    if (wbw_clear)
    if (wbw_clear)
        wbw_outTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
        wbw_outTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
    else
    else
    if (out_count_en)
    if (out_count_en)
        wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
        wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
end
end
 
 
/*always@(posedge pci_clock_in or posedge wbr_clear)
 
begin
 
    if (wbr_clear)
 
        wbr_inTransactionCount <= #`FF_DELAY 1'b0 ;
 
    else
 
        if (wbr_last_in && wbr_wallow)
 
            wbr_inTransactionCount <= #`FF_DELAY ~wbr_inTransactionCount ;
 
end
 
 
 
always@(posedge wb_clock_in or posedge wbr_clear)
 
begin
 
    if (wbr_clear)
 
        wbr_outTransactionCount <= #`FF_DELAY 1'b0 ;
 
    else
 
        if (wbr_last_out)
 
            wbr_outTransactionCount <= #`FF_DELAY ~wbr_outTransactionCount ;
 
end
 
*/
 
 
 
// synchronize transaction ready output to reading clock
// synchronize transaction ready output to reading clock
 
// transaction ready is set when incoming transaction count is not equal to outgoing transaction count (what goes in must come out logic)
 
// transaction ready is cleared when whole transaction is pulled out of fifo (otherwise it could stay set for additional cycle and result in wrong op.)
reg wbw_transaction_ready_out ;
reg wbw_transaction_ready_out ;
always@(posedge pci_clock_in or posedge wbw_clear)
always@(posedge pci_clock_in or posedge wbw_clear)
begin
begin
    if (wbw_clear)
    if (wbw_clear)
        wbw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
        wbw_transaction_ready_out <= #`FF_DELAY 1'b0 ;

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