| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:14 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:20:12 mihad
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// Revision 1.2 2001/10/05 08:20:12 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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| Line 66... |
Line 69... |
wbw_control_in,
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wbw_control_in,
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wbw_renable_in,
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wbw_renable_in,
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wbw_addr_data_out,
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wbw_addr_data_out,
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wbw_cbe_out,
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wbw_cbe_out,
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wbw_control_out,
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wbw_control_out,
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wbw_flush_in,
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// wbw_flush_in, write fifo flush not used
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wbw_almost_full_out,
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wbw_almost_full_out,
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wbw_full_out,
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wbw_full_out,
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wbw_empty_out,
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wbw_empty_out,
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wbw_transaction_ready_out,
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wbw_transaction_ready_out,
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wbr_wenable_in,
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wbr_wenable_in,
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| Line 131... |
Line 134... |
output [31:0] wbw_addr_data_out ;
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output [31:0] wbw_addr_data_out ;
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output [3:0] wbw_cbe_out ;
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output [3:0] wbw_cbe_out ;
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output [3:0] wbw_control_out ;
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output [3:0] wbw_control_out ;
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|
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// flush input
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// flush input
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input wbw_flush_in ;
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// input wbw_flush_in ; // not used
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|
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// status outputs
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// status outputs
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output wbw_almost_full_out ;
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output wbw_almost_full_out ;
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output wbw_full_out ;
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output wbw_full_out ;
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output wbw_empty_out ;
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output wbw_empty_out ;
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| Line 246... |
Line 249... |
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assign wbw_empty_out = wbw_empty ;
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assign wbw_empty_out = wbw_empty ;
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assign wbr_empty_out = wbr_empty ;
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assign wbr_empty_out = wbr_empty ;
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|
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// clear wires for fifos
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// clear wires for fifos
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wire wbw_clear = reset_in || wbw_flush_in ; // WBW_FIFO clear
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wire wbw_clear = reset_in /*|| wbw_flush_in*/ ; // WBW_FIFO clear flush not used
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wire wbr_clear = reset_in || wbr_flush_in ; // WBR_FIFO clear
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wire wbr_clear = reset_in /*|| wbr_flush_in*/ ; // WBR_FIFO clear - flush changed from asynchronous to synchronous
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|
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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Definitions of wires for connecting RAM instances
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Definitions of wires for connecting RAM instances
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-----------------------------------------------------------------------------------------------------------*/
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-----------------------------------------------------------------------------------------------------------*/
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wire [39:0] dpram_portA_output ;
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wire [39:0] dpram_portA_output ;
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| Line 408... |
Line 411... |
.rclock_in(pci_clock_in),
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.rclock_in(pci_clock_in),
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.wclock_in(wb_clock_in),
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.wclock_in(wb_clock_in),
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.renable_in(wbw_renable_in),
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.renable_in(wbw_renable_in),
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.wenable_in(wbw_wenable_in),
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.wenable_in(wbw_wenable_in),
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.reset_in(reset_in),
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.reset_in(reset_in),
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.flush_in(wbw_flush_in),
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// .flush_in(wbw_flush_in),
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.almost_full_out(wbw_almost_full_out),
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.almost_full_out(wbw_almost_full_out),
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.full_out(wbw_full_out),
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.full_out(wbw_full_out),
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.empty_out(wbw_empty),
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.empty_out(wbw_empty),
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.waddr_out(wbw_waddr),
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.waddr_out(wbw_waddr),
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.raddr_out(wbw_raddr),
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.raddr_out(wbw_raddr),
|
