| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/09/25 15:53:52 mihad
|
|
// Removed all logic from asynchronous reset network
|
|
//
|
// Revision 1.3 2002/02/01 15:25:14 mihad
|
// Revision 1.3 2002/02/01 15:25:14 mihad
|
// Repaired a few bugs, updated specification, added test bench files and design document
|
// Repaired a few bugs, updated specification, added test bench files and design document
|
//
|
//
|
// Revision 1.2 2001/10/05 08:20:12 mihad
|
// Revision 1.2 2001/10/05 08:20:12 mihad
|
// Updated all files with inclusion of timescale file for simulation purposes.
|
// Updated all files with inclusion of timescale file for simulation purposes.
|
| Line 497... |
Line 500... |
end
|
end
|
|
|
// synchronize transaction ready output to reading clock
|
// synchronize transaction ready output to reading clock
|
// transaction ready is set when incoming transaction count is not equal to outgoing transaction count (what goes in must come out logic)
|
// transaction ready is set when incoming transaction count is not equal to outgoing transaction count (what goes in must come out logic)
|
// transaction ready is cleared when whole transaction is pulled out of fifo (otherwise it could stay set for additional cycle and result in wrong op.)
|
// transaction ready is cleared when whole transaction is pulled out of fifo (otherwise it could stay set for additional cycle and result in wrong op.)
|
reg wbw_transaction_ready_out ;
|
wire wbw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
|
begin
|
meta_flop #(0) i_meta_flop_wbw_transaction_ready
|
if (wbw_clear)
|
(
|
wbw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
|
.rst_i (wbw_clear),
|
else
|
.clk_i (pci_clock_in),
|
if ( out_count_en )
|
.ld_i (out_count_en),
|
wbw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
|
.ld_val_i (1'b0),
|
else
|
.en_i (1'b1),
|
wbw_transaction_ready_out <= #`FF_DELAY inGreyCount != outGreyCount ;
|
.d_i (wbw_transaction_ready_flop_i),
|
end
|
.meta_q_o (wbw_transaction_ready_out)
|
|
) ;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
