| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.5 2002/09/30 16:03:04 mihad
|
|
// Added meta flop module for easier meta stable FF identification during synthesis
|
|
//
|
// Revision 1.4 2002/09/25 15:53:52 mihad
|
// Revision 1.4 2002/09/25 15:53:52 mihad
|
// Removed all logic from asynchronous reset network
|
// Removed all logic from asynchronous reset network
|
//
|
//
|
// Revision 1.3 2002/02/01 15:25:14 mihad
|
// Revision 1.3 2002/02/01 15:25:14 mihad
|
// Repaired a few bugs, updated specification, added test bench files and design document
|
// Repaired a few bugs, updated specification, added test bench files and design document
|
| Line 60... |
Line 63... |
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
module WBW_WBR_FIFOS(
|
module WBW_WBR_FIFOS
|
|
(
|
wb_clock_in,
|
wb_clock_in,
|
pci_clock_in,
|
pci_clock_in,
|
reset_in,
|
reset_in,
|
wbw_wenable_in,
|
wbw_wenable_in,
|
wbw_addr_data_in,
|
wbw_addr_data_in,
|
| Line 87... |
Line 91... |
wbr_data_out,
|
wbr_data_out,
|
wbr_be_out,
|
wbr_be_out,
|
wbr_control_out,
|
wbr_control_out,
|
wbr_flush_in,
|
wbr_flush_in,
|
wbr_empty_out
|
wbr_empty_out
|
|
|
|
`ifdef PCI_BIST
|
|
,
|
|
// debug chain signals
|
|
SO ,
|
|
SI ,
|
|
shift_DR ,
|
|
capture_DR ,
|
|
extest ,
|
|
tck
|
|
`endif
|
) ;
|
) ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
System inputs:
|
System inputs:
|
wb_clock_in - WISHBONE bus clock
|
wb_clock_in - WISHBONE bus clock
|
| Line 187... |
Line 202... |
// flush input
|
// flush input
|
input wbr_flush_in ;
|
input wbr_flush_in ;
|
|
|
output wbr_empty_out ;
|
output wbr_empty_out ;
|
|
|
|
`ifdef PCI_BIST
|
|
/*-----------------------------------------------------
|
|
BIST debug chain port signals
|
|
-----------------------------------------------------*/
|
|
output SO ;
|
|
input SI ;
|
|
input shift_DR ;
|
|
input capture_DR ;
|
|
input extest ;
|
|
input tck ;
|
|
`endif
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
FIFO depth parameters:
|
FIFO depth parameters:
|
WBW_DEPTH = defines WBW_FIFO depth
|
WBW_DEPTH = defines WBW_FIFO depth
|
WBR_DEPTH = defines WBR_FIFO depth
|
WBR_DEPTH = defines WBR_FIFO depth
|
WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
|
WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
|
| Line 199... |
Line 226... |
parameter WBW_DEPTH = `WBW_DEPTH ;
|
parameter WBW_DEPTH = `WBW_DEPTH ;
|
parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
|
parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
|
parameter WBR_DEPTH = `WBR_DEPTH ;
|
parameter WBR_DEPTH = `WBR_DEPTH ;
|
parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
|
parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
|
|
|
// obvious
|
|
wire vcc = 1'b1 ;
|
|
wire gnd = 1'b0 ;
|
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
|
wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
|
wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
|
wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire wbw_wallow ;
|
wire wbw_wallow ;
|
| Line 303... |
Line 326... |
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;
|
|
|
wire wbw_read_enable = 1'b1 ;
|
wire wbw_read_enable = 1'b1 ;
|
wire wbr_read_enable = 1'b1 ;
|
wire wbr_read_enable = 1'b1 ;
|
|
|
|
`ifdef PCI_BIST
|
|
wire SO_internal ; // wires for connection of debug ports on two rams
|
|
wire SI_internal = SO_internal ;
|
|
`endif
|
|
|
// instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
|
// instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
|
(
|
(
|
// Generic synchronous two-port RAM interface
|
// Generic synchronous two-port RAM interface
|
.clk_a(wb_clock_in),
|
.clk_a(wb_clock_in),
|
| Line 324... |
Line 352... |
.we_b(1'b0),
|
.we_b(1'b0),
|
.oe_b(1'b1),
|
.oe_b(1'b1),
|
.addr_b(wbw_whole_raddr),
|
.addr_b(wbw_whole_raddr),
|
.di_b(40'h00_0000_0000),
|
.di_b(40'h00_0000_0000),
|
.do_b(dpram_portB_output)
|
.do_b(dpram_portB_output)
|
|
|
|
`ifdef PCI_BIST
|
|
,
|
|
.SO (SO_internal),
|
|
.SI (SI),
|
|
.shift_DR (shift_DR),
|
|
.capture_DR (capture_DR),
|
|
.extest (extest),
|
|
.tck (tck)
|
|
`endif
|
);
|
);
|
|
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
|
(
|
(
|
// Generic synchronous two-port RAM interface
|
// Generic synchronous two-port RAM interface
|
| Line 346... |
Line 384... |
.we_b(1'b0),
|
.we_b(1'b0),
|
.oe_b(1'b1),
|
.oe_b(1'b1),
|
.addr_b(wbr_whole_raddr),
|
.addr_b(wbr_whole_raddr),
|
.di_b(40'h00_0000_0000),
|
.di_b(40'h00_0000_0000),
|
.do_b(dpram_portA_output)
|
.do_b(dpram_portA_output)
|
|
|
|
`ifdef PCI_BIST
|
|
,
|
|
.SO (SO),
|
|
.SI (SI_internal),
|
|
.shift_DR (shift_DR),
|
|
.capture_DR (capture_DR),
|
|
.extest (extest),
|
|
.tck (tck)
|
|
`endif
|
);
|
);
|
|
|
`else // RAM blocks sharing between two fifos
|
`else // RAM blocks sharing between two fifos
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
| Line 400... |
Line 448... |
.we_b(wbr_wallow),
|
.we_b(wbr_wallow),
|
.oe_b(1'b1),
|
.oe_b(1'b1),
|
.addr_b(portB_addr),
|
.addr_b(portB_addr),
|
.di_b(dpram_portB_input),
|
.di_b(dpram_portB_input),
|
.do_b(dpram_portB_output)
|
.do_b(dpram_portB_output)
|
|
|
|
`ifdef PCI_BIST
|
|
,
|
|
.SO (SO),
|
|
.SI (SI),
|
|
.shift_DR (shift_DR),
|
|
.capture_DR (capture_DR),
|
|
.extest (extest),
|
|
.tck (tck)
|
|
`endif
|
);
|
);
|
|
|
`endif
|
`endif
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
