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Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wbw_wbr_fifos.v] - Diff between revs 62 and 63

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Rev 62	Rev 63
Line 40...	Line 40...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2002/10/08 17:17:06 mihad`
	`// Added BIST signals for RAMs.`
	`//`
`// Revision 1.5 2002/09/30 16:03:04 mihad`	`// Revision 1.5 2002/09/30 16:03:04 mihad`
`// Added meta flop module for easier meta stable FF identification during synthesis`	`// Added meta flop module for easier meta stable FF identification during synthesis`
`//`	`//`
`// Revision 1.4 2002/09/25 15:53:52 mihad`	`// Revision 1.4 2002/09/25 15:53:52 mihad`
`// Removed all logic from asynchronous reset network`	`// Removed all logic from asynchronous reset network`
Line 95...	Line 98...
`wbr_empty_out`	`wbr_empty_out`

`ifdef PCI_BIST	`ifdef PCI_BIST
`,`	`,`
`// debug chain signals`	`// debug chain signals`
	`trst ,`
`SO ,`	`SO ,`
`SI ,`	`SI ,`
`shift_DR ,`	`shift_DR ,`
`capture_DR ,`	`capture_DR ,`
`extest ,`	`extest ,`
Line 206...	Line 210...

`ifdef PCI_BIST	`ifdef PCI_BIST
`/*-----------------------------------------------------`	`/*-----------------------------------------------------`
`BIST debug chain port signals`	`BIST debug chain port signals`
`-----------------------------------------------------*/`	`-----------------------------------------------------*/`
	`input trst ;`
`output SO ;`	`output SO ;`
`input SI ;`	`input SI ;`
`input shift_DR ;`	`input shift_DR ;`
`input capture_DR ;`	`input capture_DR ;`
`input extest ;`	`input extest ;`
Line 355...	Line 360...
`.di_b(40'h00_0000_0000),`	`.di_b(40'h00_0000_0000),`
`.do_b(dpram_portB_output)`	`.do_b(dpram_portB_output)`

`ifdef PCI_BIST	`ifdef PCI_BIST
`,`	`,`
	`.trst (trst),`
`.SO (SO_internal),`	`.SO (SO_internal),`
`.SI (SI),`	`.SI (SI),`
`.shift_DR (shift_DR),`	`.shift_DR (shift_DR),`
`.capture_DR (capture_DR),`	`.capture_DR (capture_DR),`
`.extest (extest),`	`.extest (extest),`
Line 387...	Line 393...
`.di_b(40'h00_0000_0000),`	`.di_b(40'h00_0000_0000),`
`.do_b(dpram_portA_output)`	`.do_b(dpram_portA_output)`

`ifdef PCI_BIST	`ifdef PCI_BIST
`,`	`,`
	`.trst (trst),`
`.SO (SO),`	`.SO (SO),`
`.SI (SI_internal),`	`.SI (SI_internal),`
`.shift_DR (shift_DR),`	`.shift_DR (shift_DR),`
`.capture_DR (capture_DR),`	`.capture_DR (capture_DR),`
`.extest (extest),`	`.extest (extest),`
Line 451...	Line 458...
`.di_b(dpram_portB_input),`	`.di_b(dpram_portB_input),`
`.do_b(dpram_portB_output)`	`.do_b(dpram_portB_output)`

`ifdef PCI_BIST	`ifdef PCI_BIST
`,`	`,`
	`.trst (trst),`
`.SO (SO),`	`.SO (SO),`
`.SI (SI),`	`.SI (SI),`
`.shift_DR (shift_DR),`	`.shift_DR (shift_DR),`
`.capture_DR (capture_DR),`	`.capture_DR (capture_DR),`
`.extest (extest),`	`.extest (extest),`

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wbw_wbr_fifos.v] - Diff between revs 62 and 63