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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [pci_behaviorial_master.v] - Diff between revs 19 and 35

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//===========================================================================
//===========================================================================
// $Id: pci_behaviorial_master.v,v 1.1 2002-02-01 15:07:51 mihad Exp $
// $Id: pci_behaviorial_master.v,v 1.2 2002-03-21 07:35:50 mihad Exp $
//
//
// Copyright 2001 Blue Beaver.  All Rights Reserved.
// Copyright 2001 Blue Beaver.  All Rights Reserved.
//
//
// Summary:  A PCI Behaviorial Master.  This module accepts commands from
// Summary:  A PCI Behaviorial Master.  This module accepts commands from
//           the top-level Stimulus generator.  Based on arguments supplied
//           the top-level Stimulus generator.  Based on arguments supplied
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// Complain if SERR caused by address parity error not seen when expected
// Complain if SERR caused by address parity error not seen when expected
// complain if data parity error not seen when expected
// complain if data parity error not seen when expected
//
//
//===========================================================================
//===========================================================================
 
 
`timescale 1ns/1ps
// synopsys translate_off
 
`include "timescale.v"
 
// synopsys translate_on
 
 
module pci_behaviorial_master (
module pci_behaviorial_master (
  ad_now, ad_prev, master_ad_out, master_ad_oe,
  ad_now, ad_prev, master_ad_out, master_ad_oe,
  master_cbe_l_out, master_cbe_oe,
  master_cbe_l_out, master_cbe_oe,
  calc_input_parity_prev,
  calc_input_parity_prev,

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