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//===========================================================================
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//===========================================================================
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// $Id: pci_behaviorial_target.v,v 1.1 2002-02-01 15:07:51 mihad Exp $
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// $Id: pci_behaviorial_target.v,v 1.2 2002-02-19 16:32:29 mihad Exp $
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//
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//
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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//
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//
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// Summary: A PCI Behaviorial Target. This module receives commands over
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// Summary: A PCI Behaviorial Target. This module receives commands over
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// the PCI Bus. The PCI Master encodes commands in the middle
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// the PCI Bus. The PCI Master encodes commands in the middle
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end
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end
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end
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end
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end
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end
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// Tasks to manage the small SRAM visible in Memory Space
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// Tasks to manage the small SRAM visible in Memory Space
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reg [PCI_BUS_DATA_RANGE:0] Test_Device_Mem [0:255]; // address limits, not bits in address
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reg [PCI_BUS_DATA_RANGE:0] Test_Device_Mem [0:1023]; // address limits, not bits in address
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// Tasks can't have local storage! have to be module global
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// Tasks can't have local storage! have to be module global
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reg [7:0] sram_addr;
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reg [9:0] sram_addr;
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task Init_Test_Device_SRAM;
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task Init_Test_Device_SRAM;
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begin
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begin
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for (sram_addr = 8'h00; sram_addr < 8'hFF; sram_addr = sram_addr + 8'h01)
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for (sram_addr = 10'h000; sram_addr < 10'h3FF; sram_addr = sram_addr + 10'h001)
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begin
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begin
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Test_Device_Mem[sram_addr] = `BUS_IMPOSSIBLE_VALUE;
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Test_Device_Mem[sram_addr] = `BUS_IMPOSSIBLE_VALUE;
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end
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end
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sram_addr = 10'h3FF; // maximum value must also be written!
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Test_Device_Mem[sram_addr] = `BUS_IMPOSSIBLE_VALUE;
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end
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end
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endtask
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endtask
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task Read_Test_Device_SRAM;
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task Read_Test_Device_SRAM;
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input [9:2] sram_address;
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input [11:2] sram_address;
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input [PCI_BUS_CBE_RANGE:0] byte_sel ;
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input [PCI_BUS_CBE_RANGE:0] byte_sel ;
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output [PCI_BUS_DATA_RANGE:0] target_read_data;
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output [PCI_BUS_DATA_RANGE:0] target_read_data;
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reg [PCI_BUS_DATA_RANGE:0] temp_val ;
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reg [PCI_BUS_DATA_RANGE:0] temp_val ;
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begin
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begin
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temp_val = Test_Device_Mem[sram_address] ;
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temp_val = Test_Device_Mem[sram_address] ;
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endtask
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endtask
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// Tasks can't have local storage! have to be module global
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// Tasks can't have local storage! have to be module global
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reg [PCI_BUS_DATA_RANGE:0] sram_temp;
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reg [PCI_BUS_DATA_RANGE:0] sram_temp;
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task Write_Test_Device_SRAM;
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task Write_Test_Device_SRAM;
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input [9:2] sram_address;
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input [11:2] sram_address;
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input [PCI_BUS_DATA_RANGE:0] master_write_data;
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input [PCI_BUS_DATA_RANGE:0] master_write_data;
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input [PCI_BUS_CBE_RANGE:0] master_mask_l;
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input [PCI_BUS_CBE_RANGE:0] master_mask_l;
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begin
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begin
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sram_temp = Test_Device_Mem[sram_address];
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sram_temp = Test_Device_Mem[sram_address];
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sram_temp[7:0] = (~master_mask_l[0]) ? master_write_data[7:0] : sram_temp[7:0];
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sram_temp[7:0] = (~master_mask_l[0]) ? master_write_data[7:0] : sram_temp[7:0];
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// Store data from PCI bus into SRAM, and increment Write Pointer
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// Store data from PCI bus into SRAM, and increment Write Pointer
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task Capture_SRAM_Data_From_AD_Bus;
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task Capture_SRAM_Data_From_AD_Bus;
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input [PCI_BUS_DATA_RANGE:0] master_write_data;
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input [PCI_BUS_DATA_RANGE:0] master_write_data;
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input [PCI_BUS_CBE_RANGE:0] master_mask_l;
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input [PCI_BUS_CBE_RANGE:0] master_mask_l;
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begin
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begin
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Write_Test_Device_SRAM (hold_target_address[9:2],
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Write_Test_Device_SRAM (hold_target_address[11:2],
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master_write_data[PCI_BUS_DATA_RANGE:0], master_mask_l[PCI_BUS_CBE_RANGE:0]);
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master_write_data[PCI_BUS_DATA_RANGE:0], master_mask_l[PCI_BUS_CBE_RANGE:0]);
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hold_target_address[9:2] = hold_target_address[9:2] + 8'h01; // addr++
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hold_target_address[11:2] = hold_target_address[11:2] + 10'h001; // addr++
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end
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end
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endtask
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endtask
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// Drive SRAM Data onto AD bus, and increment Read Pointer
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// Drive SRAM Data onto AD bus, and increment Read Pointer
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task Fetch_SRAM_Data_For_Read_Onto_AD_Bus;
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task Fetch_SRAM_Data_For_Read_Onto_AD_Bus;
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output [PCI_BUS_DATA_RANGE:0] target_read_data;
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output [PCI_BUS_DATA_RANGE:0] target_read_data;
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begin
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begin
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Read_Test_Device_SRAM (hold_target_address[9:2], ~cbe_l_now, target_read_data[PCI_BUS_DATA_RANGE:0]);
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Read_Test_Device_SRAM (hold_target_address[11:2], ~cbe_l_now, target_read_data[PCI_BUS_DATA_RANGE:0]);
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hold_target_address[9:2] = hold_target_address[9:2] + 8'h01; // addr++
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hold_target_address[11:2] = hold_target_address[11:2] + 10'h001; // addr++
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end
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end
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endtask
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endtask
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// The target is able to execute Delayed Reads,
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// The target is able to execute Delayed Reads,
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// See the PCI Local Bus Spec Revision 2.2 section 3.3.3.3
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// See the PCI Local Bus Spec Revision 2.2 section 3.3.3.3
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