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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [pci_behaviorial_target.v] - Diff between revs 26 and 35

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//===========================================================================
//===========================================================================
// $Id: pci_behaviorial_target.v,v 1.2 2002-02-19 16:32:29 mihad Exp $
// $Id: pci_behaviorial_target.v,v 1.3 2002-03-21 07:35:50 mihad Exp $
//
//
// Copyright 2001 Blue Beaver.  All Rights Reserved.
// Copyright 2001 Blue Beaver.  All Rights Reserved.
//
//
// Summary:  A PCI Behaviorial Target.  This module receives commands over
// Summary:  A PCI Behaviorial Target.  This module receives commands over
//           the PCI Bus.  The PCI Master encodes commands in the middle
//           the PCI Bus.  The PCI Master encodes commands in the middle
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// Complain if address parity error not seen when expected
// Complain if address parity error not seen when expected
// Complain if data parity error not seen when expected
// Complain if data parity error not seen when expected
//
//
//===========================================================================
//===========================================================================
 
 
`timescale 1ns/1ps
// synopsys translate_off
 
`include "timescale.v"
 
// synopsys translate_on
 
 
module pci_behaviorial_target (
module pci_behaviorial_target (
  ad_now, ad_prev, target_ad_out, target_ad_oe,
  ad_now, ad_prev, target_ad_out, target_ad_oe,
  cbe_l_now, cbe_l_prev, calc_input_parity_prev, par_now, par_prev,
  cbe_l_now, cbe_l_prev, calc_input_parity_prev, par_now, par_prev,
  frame_now, frame_prev, irdy_now, irdy_prev,
  frame_now, frame_prev, irdy_now, irdy_prev,

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