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//===========================================================================
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//===========================================================================
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// $Id: pci_behaviorial_target.v,v 1.3 2002-03-21 07:35:50 mihad Exp $
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// $Id: pci_behaviorial_target.v,v 1.4 2002-08-13 11:03:51 mihad Exp $
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//
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//
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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//
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//
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// Summary: A PCI Behaviorial Target. This module receives commands over
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// Summary: A PCI Behaviorial Target. This module receives commands over
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// the PCI Bus. The PCI Master encodes commands in the middle
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// the PCI Bus. The PCI Master encodes commands in the middle
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endtask
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endtask
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// Drive SRAM Data onto AD bus, and increment Read Pointer
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// Drive SRAM Data onto AD bus, and increment Read Pointer
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task Fetch_SRAM_Data_For_Read_Onto_AD_Bus;
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task Fetch_SRAM_Data_For_Read_Onto_AD_Bus;
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output [PCI_BUS_DATA_RANGE:0] target_read_data;
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output [PCI_BUS_DATA_RANGE:0] target_read_data;
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reg fetch_from0 ;
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begin
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begin
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Read_Test_Device_SRAM (hold_target_address[11:2], ~cbe_l_now, target_read_data[PCI_BUS_DATA_RANGE:0]);
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fetch_from0 = (hold_target_command == PCI_COMMAND_INTERRUPT_ACKNOWLEDGE) ;
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Read_Test_Device_SRAM (fetch_from0 ? 0 : hold_target_address[11:2], ~cbe_l_now, target_read_data[PCI_BUS_DATA_RANGE:0]);
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hold_target_address[11:2] = hold_target_address[11:2] + 10'h001; // addr++
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hold_target_address[11:2] = hold_target_address[11:2] + 10'h001; // addr++
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end
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end
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endtask
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endtask
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// The target is able to execute Delayed Reads,
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// The target is able to execute Delayed Reads,
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& (ad_now[1:0] == 2'b00) )
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& (ad_now[1:0] == 2'b00) )
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begin
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begin
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Execute_Target_PCI_Ref (`TEST_TARGET_DOING_CONFIG_WRITE,
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Execute_Target_PCI_Ref (`TEST_TARGET_DOING_CONFIG_WRITE,
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saw_fast_back_to_back);
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saw_fast_back_to_back);
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end
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end
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else if (~frame_prev & frame_now & Target_En
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else if (~frame_prev & frame_now & Target_En &
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`ifdef SIMULTANEOUS_MASTER_TARGET
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(
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// Don't check for reads to self
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(cbe_l_now[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_INTERRUPT_ACKNOWLEDGE) |
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`else // SIMULTANEOUS_MASTER_TARGET
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(
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// Check for, and don't respond to, reads to self
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(
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`endif //SIMULTANEOUS_MASTER_TARGET
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(cbe_l_now[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_READ)
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& ( (cbe_l_now[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_READ)
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| (cbe_l_now[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_READ_MULTIPLE)
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| (cbe_l_now[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_READ_MULTIPLE)
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| (cbe_l_now[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_READ_LINE) )
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| (cbe_l_now[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_MEMORY_READ_LINE)
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& ( (ad_now[`PCI_BASE_ADDR0_MATCH_RANGE] == BAR0[`PCI_BASE_ADDR0_MATCH_RANGE])
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)
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&
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(
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(ad_now[`PCI_BASE_ADDR0_MATCH_RANGE] == BAR0[`PCI_BASE_ADDR0_MATCH_RANGE])
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`ifdef PCI_BASE_ADDR1_MATCH_ENABLE
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`ifdef PCI_BASE_ADDR1_MATCH_ENABLE
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| (ad_now[`PCI_BASE_ADDR1_MATCH_RANGE] == BAR1[`PCI_BASE_ADDR1_MATCH_RANGE])
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| (ad_now[`PCI_BASE_ADDR1_MATCH_RANGE] == BAR1[`PCI_BASE_ADDR1_MATCH_RANGE])
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`endif // PCI_BASE_ADDR1_MATCH_ENABLE
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`endif // PCI_BASE_ADDR1_MATCH_ENABLE
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) )
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)
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)
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)
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)
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begin
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begin
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Execute_Target_PCI_Ref (`TEST_TARGET_DOING_SRAM_READ,
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Execute_Target_PCI_Ref (`TEST_TARGET_DOING_SRAM_READ,
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saw_fast_back_to_back);
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saw_fast_back_to_back);
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end
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end
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else if (~frame_prev & frame_now & (idsel_now == 1'b1)
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else if (~frame_prev & frame_now & (idsel_now == 1'b1)
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