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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [pci_blue_arbiter.v] - Diff between revs 15 and 35

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//===========================================================================
//===========================================================================
// $Id: pci_blue_arbiter.v,v 1.1 2002-02-01 13:39:43 mihad Exp $
// $Id: pci_blue_arbiter.v,v 1.2 2002-03-21 07:35:50 mihad Exp $
//
//
// Copyright 2001 Blue Beaver.  All Rights Reserved.
// Copyright 2001 Blue Beaver.  All Rights Reserved.
//
//
// Summary:  A synthesizable PCI Arbiter.  This will have 4 external PCI
// Summary:  A synthesizable PCI Arbiter.  This will have 4 external PCI
//           Request/Grant pairs and one internal Request/Grant Pair.
//           Request/Grant pairs and one internal Request/Grant Pair.
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//        the device has started a reference before granting to a new
//        the device has started a reference before granting to a new
//        device.  If no other requests are pending, the grant stays put.
//        device.  If no other requests are pending, the grant stays put.
//
//
//===========================================================================
//===========================================================================
 
 
`timescale 1ns/1ps
// synopsys translate_off
 
`include "timescale.v"
 
// synopsys translate_on
 
 
// Allows printing of Arbiter Debug info.  Usually not defined
// Allows printing of Arbiter Debug info.  Usually not defined
//`define PCI_TRACE_ARB 1
//`define PCI_TRACE_ARB 1
 
 
module pci_blue_arbiter (
module pci_blue_arbiter (

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