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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [pci_blue_arbiter.v] - Diff between revs 15 and 35
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//===========================================================================
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//===========================================================================
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// $Id: pci_blue_arbiter.v,v 1.1 2002-02-01 13:39:43 mihad Exp $
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// $Id: pci_blue_arbiter.v,v 1.2 2002-03-21 07:35:50 mihad Exp $
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//
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//
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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//
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//
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// Summary: A synthesizable PCI Arbiter. This will have 4 external PCI
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// Summary: A synthesizable PCI Arbiter. This will have 4 external PCI
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// Request/Grant pairs and one internal Request/Grant Pair.
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// Request/Grant pairs and one internal Request/Grant Pair.
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// the device has started a reference before granting to a new
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// the device has started a reference before granting to a new
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// device. If no other requests are pending, the grant stays put.
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// device. If no other requests are pending, the grant stays put.
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//
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//
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//===========================================================================
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//===========================================================================
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`timescale 1ns/1ps
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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// Allows printing of Arbiter Debug info. Usually not defined
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// Allows printing of Arbiter Debug info. Usually not defined
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//`define PCI_TRACE_ARB 1
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//`define PCI_TRACE_ARB 1
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module pci_blue_arbiter (
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module pci_blue_arbiter (
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