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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//// ===================================================================== ////
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//// ===================================================================== ////
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//// Following PCI_USER_CONSTANTS are just for regression testing purposes ////
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//// Following PCI_USER_CONSTANTS are just for regression testing purposes ////
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//`define WB_ARTISAN_SDP
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//`define WB_ARTISAN_SDP
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//`define PCI_ARTISAN_SDP
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//`define PCI_ARTISAN_SDP
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`endif
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`endif
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`else
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`else
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`ifdef REGR_FIFO_LARGE_GENERIC // without any parameters only (generic)
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`ifdef REGR_FIFO_LARGE_GENERIC // without any parameters only (generic)
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`define WBW_ADDR_LENGTH 10
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`define WBW_ADDR_LENGTH 9
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`define WBR_ADDR_LENGTH 10
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`define WBR_ADDR_LENGTH 9
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`define PCIW_ADDR_LENGTH 10
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`define PCIW_ADDR_LENGTH 9
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`define PCIR_ADDR_LENGTH 10
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`define PCIR_ADDR_LENGTH 9
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//`define FPGA
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//`define FPGA
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//`define XILINX
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//`define XILINX
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//`define WB_RAM_DONT_SHARE
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//`define WB_RAM_DONT_SHARE
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`define WB_XILINX_RAMB4
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`define WB_XILINX_RAMB4
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//`define PCI_XILINX_DIST_RAM
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//`define PCI_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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`endif
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`endif
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`else
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`else
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`define PCI_FIFO_RAM_ADDR_LENGTH 11 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define PCI_FIFO_RAM_ADDR_LENGTH 10 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 11 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 10 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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//`define WB_ARTISAN_SDP
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//`define WB_ARTISAN_SDP
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//`define PCI_ARTISAN_SDP
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//`define PCI_ARTISAN_SDP
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`endif
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`endif
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`else
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`else
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`endif
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`endif
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// smaller the number here, faster the decoder operation
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// smaller the number here, faster the decoder operation
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`ifdef WB_DECODE_MIN
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`ifdef WB_DECODE_MIN
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`define WB_NUM_OF_DEC_ADDR_LINES 3
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`define WB_NUM_OF_DEC_ADDR_LINES 4
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`else
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`else
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`ifdef WB_DECODE_MED
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`ifdef WB_DECODE_MED
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`define WB_NUM_OF_DEC_ADDR_LINES 12
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`define WB_NUM_OF_DEC_ADDR_LINES 12
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`else
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`else
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`ifdef WB_DECODE_MAX
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`ifdef WB_DECODE_MAX
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// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
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// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
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`ifdef WB_CNF_BASE_ZERO
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`ifdef WB_CNF_BASE_ZERO
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`define WB_CONFIGURATION_BASE 20'h0000_0
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`define WB_CONFIGURATION_BASE 20'h0000_0
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`else
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`else
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`define WB_CONFIGURATION_BASE 20'hF000_0
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`define WB_CONFIGURATION_BASE 20'hB000_0
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`endif
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`endif
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
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[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
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Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
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Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
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Line 283... |
`define HEADER_DEVICE_ID 16'h0001
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`define HEADER_DEVICE_ID 16'h0001
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`define HEADER_REVISION_ID 8'h01
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`define HEADER_REVISION_ID 8'h01
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// MAX Retry counter value for WISHBONE Master state-machine
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// MAX Retry counter value for WISHBONE Master state-machine
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// This value is 8-bit because of 8-bit retry counter !!!
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// This value is 8-bit because of 8-bit retry counter !!!
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`ifdef WB_RETRY_MAX
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`define WB_RTY_CNT_MAX 8'hff
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`define WB_RTY_CNT_MAX 8'hff
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`else
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`define WB_RTY_CNT_MAX 8'h1c
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`endif
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/////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////
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//// ======================================================================= ////
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//// ======================================================================= ////
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//// Following PCI_TESTBENC_DEFINES are just for regression testing purposes ////
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//// Following PCI_TESTBENC_DEFINES are just for regression testing purposes ////
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//// (script for running regression is prepared for NC-Sim) ////
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//// (script for running regression is prepared for NC-Sim) ////
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Line 301... |
`define WB_FREQ 0.01
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`define WB_FREQ 0.01
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`else
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`else
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`ifdef WB_CLK66
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`ifdef WB_CLK66
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`define WB_FREQ 0.066
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`define WB_FREQ 0.066
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`else
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`else
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`ifdef WB_CLK100
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`ifdef WB_CLK220
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`define WB_FREQ 0.1
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`define WB_FREQ 0.22
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`endif
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`endif
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`endif
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`endif
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`endif
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`endif
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// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
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// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
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`define TAR0_BASE_ADDR_0 32'h1000_0000
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`define TAR0_BASE_ADDR_0 32'h1000_0000
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`define TAR0_BASE_ADDR_1 32'h2000_0000
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`define TAR0_BASE_ADDR_1 32'h2000_0000
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`define TAR0_BASE_ADDR_2 32'h3000_0000
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`define TAR0_BASE_ADDR_2 32'h4000_0000
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`define TAR0_BASE_ADDR_3 32'h4000_0000
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`define TAR0_BASE_ADDR_3 32'h6000_0000
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`define TAR0_BASE_ADDR_4 32'h5000_0000
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`define TAR0_BASE_ADDR_4 32'h8000_0000
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`define TAR0_BASE_ADDR_5 32'h6000_0000
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`define TAR0_BASE_ADDR_5 32'hA000_0000
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`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
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`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
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`define TAR0_ADDR_MASK_1 32'hFFFF_F000
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`define TAR0_ADDR_MASK_1 32'hFFFF_F000
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`define TAR0_ADDR_MASK_2 32'hFFFF_F000
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`define TAR0_ADDR_MASK_2 32'hFFFF_F000
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`define TAR0_ADDR_MASK_3 32'hFFFF_F000
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`define TAR0_ADDR_MASK_3 32'hFFFF_F000
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`define TAR0_ADDR_MASK_4 32'hFFFF_F000
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`define TAR0_ADDR_MASK_4 32'hFFFF_F000
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`define TAR0_ADDR_MASK_5 32'hFFFF_F000
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`define TAR0_ADDR_MASK_5 32'hFFFF_F000
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`define TAR0_TRAN_ADDR_0 32'h5000_0000 // when BA0 is used to access configuration space, this is NOT important!
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`define TAR0_TRAN_ADDR_0 32'hC000_0000 // when BA0 is used to access configuration space, this is NOT important!
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`define TAR0_TRAN_ADDR_1 32'h4000_0000
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`define TAR0_TRAN_ADDR_1 32'hA000_0000
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`define TAR0_TRAN_ADDR_2 32'h3000_0000
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`define TAR0_TRAN_ADDR_2 32'h8000_0000
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`define TAR0_TRAN_ADDR_3 32'h2000_0000
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`define TAR0_TRAN_ADDR_3 32'h6000_0000
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`define TAR0_TRAN_ADDR_4 32'h1000_0000
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`define TAR0_TRAN_ADDR_4 32'h4000_0000
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`define TAR0_TRAN_ADDR_5 32'h0000_0000
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`define TAR0_TRAN_ADDR_5 32'h2000_0000
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// values of image registers of PCI behavioral target devices !
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// values of image registers of PCI behavioral target devices !
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`define BEH_TAR1_MEM_START 32'h7000_0000
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`define BEH_TAR1_MEM_START 32'hC000_0000
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`define BEH_TAR1_MEM_END 32'h7000_0FFF
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`define BEH_TAR1_MEM_END 32'hC000_0FFF
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`define BEH_TAR1_IO_START 32'h8000_0001
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`define BEH_TAR1_IO_START 32'hD000_0001
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`define BEH_TAR1_IO_END 32'h8000_0FFF
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`define BEH_TAR1_IO_END 32'hD000_0FFF
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`define BEH_TAR2_MEM_START 32'h9000_0000
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`define BEH_TAR2_MEM_START 32'hE000_0000
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`define BEH_TAR2_MEM_END 32'h9000_0FFF
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`define BEH_TAR2_MEM_END 32'hE000_0FFF
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`define BEH_TAR2_IO_START 32'hA000_0001
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`define BEH_TAR2_IO_START 32'hF000_0001
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`define BEH_TAR2_IO_END 32'hA000_0FFF
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`define BEH_TAR2_IO_END 32'hF000_0FFF
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/*=======================================================================================
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/*=======================================================================================
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Following defines are used in a script file for regression testing !!!
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Following defines are used in a script file for regression testing !!!
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=========================================================================================
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=========================================================================================
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