| Line 700... |
Line 700... |
begin
|
begin
|
// fill write memories with random data
|
// fill write memories with random data
|
for( temp_index = 0; temp_index <=1023; temp_index = temp_index + 1 )
|
for( temp_index = 0; temp_index <=1023; temp_index = temp_index + 1 )
|
begin
|
begin
|
wmem_data[temp_index[9:0]] = $random ;
|
wmem_data[temp_index[9:0]] = $random ;
|
|
# 1;
|
wio_data[temp_index[9:0]] = $random ;
|
wio_data[temp_index[9:0]] = $random ;
|
|
# 1;
|
end
|
end
|
// fill WB slave behavioral MEMORY
|
// fill WB slave behavioral MEMORY
|
for( temp_index = 0; temp_index <=65535; temp_index = temp_index + 1 )
|
for( temp_index = 0; temp_index <=65535; temp_index = temp_index + 1 )
|
begin
|
begin
|
wishbone_slave.wb_memory[temp_index[15:0]] = $random ;
|
wishbone_slave.wb_memory[temp_index[15:0]] = $random ;
|
| Line 4326... |
Line 4328... |
|
|
test_name = "INTERRUPT REQUEST ASSERTION AFTER PARITY ERROR" ;
|
test_name = "INTERRUPT REQUEST ASSERTION AFTER PARITY ERROR" ;
|
// interrupt should also be present
|
// interrupt should also be present
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
|
|
if ( INT_O !== 1 )
|
if ( INT_O !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 4339... |
Line 4343... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 4428... |
Line 4434... |
|
|
config_write( isr_offset, temp_val1, 4'hF, ok ) ;
|
config_write( isr_offset, temp_val1, 4'hF, ok ) ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
|
|
if ( INT_O !== 0 )
|
if ( INT_O !== 0 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 4441... |
Line 4449... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 4501... |
Line 4511... |
test_name = "INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLED" ;
|
test_name = "INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLED" ;
|
|
|
// interrupts should not be present
|
// interrupts should not be present
|
`ifdef HOST
|
`ifdef HOST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge pci_clock) ;
|
|
repeat( 4 )
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 0 )
|
if ( INT_O !== 0 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity Error response was disabled, but bridge asserted interrupt because of parity error!") ;
|
$display("Parity Error response was disabled, but bridge asserted interrupt because of parity error!") ;
|
| Line 4513... |
Line 4525... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat( 4 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity Error response was disabled, but bridge asserted interrupt because of parity error!") ;
|
$display("Parity Error response was disabled, but bridge asserted interrupt because of parity error!") ;
|
| Line 4892... |
Line 4906... |
|
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR" ;
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR" ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 0 )
|
if ( INT_O !== 0 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Address Parity Error was presented on PCI, SERR int. en. was not set, but INT REQ was signalled on WB bus!") ;
|
$display("Address Parity Error was presented on PCI, SERR int. en. was not set, but INT REQ was signalled on WB bus!") ;
|
| Line 4904... |
Line 4920... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 5016... |
Line 5034... |
|
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI" ;
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI" ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 1 )
|
if ( INT_O !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Address Parity error just presented on PCI should trigger an interrupt request, but no request detected!") ;
|
$display("Address Parity error just presented on PCI should trigger an interrupt request, but no request detected!") ;
|
| Line 5028... |
Line 5048... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 5150... |
Line 5172... |
|
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI" ;
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI" ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 1 )
|
if ( INT_O !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Address Parity error just presented on PCI should trigger an interrupt request, but no request detected!") ;
|
$display("Address Parity error just presented on PCI should trigger an interrupt request, but no request detected!") ;
|
| Line 5162... |
Line 5186... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 5284... |
Line 5310... |
|
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI" ;
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI" ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 1 )
|
if ( INT_O !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Address Parity error just presented on PCI should trigger an interrupt request, but no request detected!") ;
|
$display("Address Parity error just presented on PCI should trigger an interrupt request, but no request detected!") ;
|
| Line 5296... |
Line 5324... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 5418... |
Line 5448... |
|
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI" ;
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI" ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 1 )
|
if ( INT_O !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Address Parity error just presented on PCI should trigger an interrupt request, but no request detected!") ;
|
$display("Address Parity error just presented on PCI should trigger an interrupt request, but no request detected!") ;
|
| Line 5430... |
Line 5462... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 5552... |
Line 5586... |
test_ok ;
|
test_ok ;
|
|
|
test_name = "INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLED" ;
|
test_name = "INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLED" ;
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 0 )
|
if ( INT_O !== 0 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Address Parity error just presented on PCI shouldn't trigger an interrupt request!") ;
|
$display("Address Parity error just presented on PCI shouldn't trigger an interrupt request!") ;
|
| Line 5564... |
Line 5600... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat ( 4 )
|
repeat ( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat (4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 5773... |
Line 5811... |
|
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR" ;
|
test_name = "INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR" ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 0 )
|
if ( INT_O !== 0 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Address Parity Error was presented on PCI, SERR int. en. was not set, but INT REQ was signalled on WB bus!") ;
|
$display("Address Parity Error was presented on PCI, SERR int. en. was not set, but INT REQ was signalled on WB bus!") ;
|
| Line 5785... |
Line 5825... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 5869... |
Line 5911... |
test_ok ;
|
test_ok ;
|
|
|
test_name = "INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITE" ;
|
test_name = "INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITE" ;
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 0 )
|
if ( INT_O !== 0 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Interrupt request asserted for no reason!") ;
|
$display("Interrupt request asserted for no reason!") ;
|
| Line 5881... |
Line 5925... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 6030... |
Line 6076... |
test_fail("Bridge failed to assert PERR on write reference to bridge's target") ;
|
test_fail("Bridge failed to assert PERR on write reference to bridge's target") ;
|
|
|
test_name = "INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERROR" ;
|
test_name = "INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERROR" ;
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 0 )
|
if ( INT_O !== 0 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Interrupt request asserted for no reason!") ;
|
$display("Interrupt request asserted for no reason!") ;
|
| Line 6042... |
Line 6090... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat ( 4 )
|
repeat ( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat (4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 6191... |
Line 6241... |
|
|
|
|
test_name = "INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGET" ;
|
test_name = "INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGET" ;
|
`ifdef HOST
|
`ifdef HOST
|
repeat(4)
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
if ( INT_O !== 0 )
|
if ( INT_O !== 0 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Interrupt request asserted for no reason!") ;
|
$display("Interrupt request asserted for no reason!") ;
|
| Line 6203... |
Line 6255... |
else
|
else
|
test_ok ;
|
test_ok ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
repeat( 4 )
|
repeat( 4 )
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( INTA !== 1 )
|
if ( INTA !== 1 )
|
begin
|
begin
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
$display("Parity checker testing failed! Time %t ", $time) ;
|
| Line 7855... |
Line 7909... |
$display("Transaction ordering test failed! WB Master didn't start expected transaction on WB bus! Time %t ", $time) ;
|
$display("Transaction ordering test failed! WB Master didn't start expected transaction on WB bus! Time %t ", $time) ;
|
test_fail("WB Master didn't start expected transaction on WB bus") ;
|
test_fail("WB Master didn't start expected transaction on WB bus") ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
while ( FRAME !== 1 || IRDY !== 1 )
|
pci_transaction_progress_monitor( wb_target_address + 12, `BC_MEM_WRITE, 0, 0, 1'b1, 1'b0, 1'b0, ok ) ;
|
@(posedge pci_clock) ;
|
// while ( FRAME === 0 || IRDY === 0 )
|
|
// @(posedge pci_clock) ;
|
|
|
// enable response in PCI target
|
// enable response in PCI target
|
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
|
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
|
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 1 ;
|
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 1 ;
|
|
|
| Line 8003... |
Line 8058... |
$display("Transaction ordering test failed! WB Master didn't start expected transaction on WB bus! Time %t ", $time) ;
|
$display("Transaction ordering test failed! WB Master didn't start expected transaction on WB bus! Time %t ", $time) ;
|
test_fail("WB Master didn't start expected transaction on WB bus") ;
|
test_fail("WB Master didn't start expected transaction on WB bus") ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
while ( FRAME !== 1 || IRDY !== 1 )
|
pci_transaction_progress_monitor( wb_target_address, `BC_MEM_WRITE, 0, 0, 1'b1, 1'b0, 1'b0, ok ) ;
|
@(posedge pci_clock) ;
|
// while ( FRAME === 0 || IRDY === 0 )
|
|
// @(posedge pci_clock) ;
|
|
|
// enable response in PCI target
|
// enable response in PCI target
|
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
|
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
|
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 1 ;
|
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 1 ;
|
|
|
| Line 8214... |
Line 8270... |
$display("Transaction ordering test failed! WB Slave didn't respond with retry on delayed read request! Time %t ", $time) ;
|
$display("Transaction ordering test failed! WB Slave didn't respond with retry on delayed read request! Time %t ", $time) ;
|
test_fail("WB Slave didn't respond as expected to delayed read request") ;
|
test_fail("WB Slave didn't respond as expected to delayed read request") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
|
|
@(posedge pci_clock) ;
|
pci_transaction_progress_monitor( write_data`WRITE_ADDRESS, `BC_MEM_WRITE, 0, 0, 1'b1, 1'b0, 1'b1, ok ) ;
|
while ( FRAME !== 1 || IRDY !== 1 )
|
// while ( FRAME === 0 || IRDY === 0 )
|
@(posedge pci_clock) ;
|
// @(posedge pci_clock) ;
|
|
|
// set the target to normal completion
|
// set the target to normal completion
|
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
|
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
|
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 1 ;
|
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 1 ;
|
|
|
| Line 8449... |
Line 8505... |
);
|
);
|
|
|
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
|
|
// wait for current cycle to finish on WB
|
// wait for current cycle to finish on WB
|
@(posedge wb_clock) ;
|
wb_transaction_progress_monitor( pci_image_base + 12, 1'b1, 0, 1'b1, ok ) ;
|
while( CYC_O === 1 )
|
// @(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
// while( CYC_O === 1 )
|
|
// @(posedge wb_clock) ;
|
|
|
// set slave response to acknowledge
|
// set slave response to acknowledge
|
wishbone_slave.cycle_response(3'b100, tb_subseq_waits, 8'h0);
|
wishbone_slave.cycle_response(3'b100, tb_subseq_waits, 8'h0);
|
|
|
wb_transaction_progress_monitor( pci_image_base + 12, 1'b1, 1, 1'b1, ok ) ;
|
wb_transaction_progress_monitor( pci_image_base + 12, 1'b1, 1, 1'b1, ok ) ;
|
| Line 8630... |
Line 8687... |
|
|
if ( doing_fast_back_to_back !== 1 )
|
if ( doing_fast_back_to_back !== 1 )
|
begin
|
begin
|
while ( (FRAME !== 1) && (deadlock_counter < deadlock_max_val) )
|
while ( (FRAME !== 1) && (deadlock_counter < deadlock_max_val) )
|
begin
|
begin
|
|
if ( (IRDY == 0) && ((TRDY == 0) || (STOP == 0)) )
|
|
deadlock_counter = 0 ;
|
|
else
|
deadlock_counter = deadlock_counter + 1 ;
|
deadlock_counter = deadlock_counter + 1 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
end
|
end
|
if ( FRAME !== 1 )
|
if ( FRAME !== 1 )
|
begin
|
begin
|
| Line 8829... |
Line 8889... |
begin:wait_start
|
begin:wait_start
|
deadlock_counter = 0 ;
|
deadlock_counter = 0 ;
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
while ( (CYC_O !== 0 && CYC_O_previous !== 0) && (deadlock_counter < deadlock_max_val) )
|
while ( (CYC_O !== 0 && CYC_O_previous !== 0) && (deadlock_counter < deadlock_max_val) )
|
begin
|
begin
|
|
if ((!STB_O) || (!ACK_I && !RTY_I && !ERR_I))
|
deadlock_counter = deadlock_counter + 1 ;
|
deadlock_counter = deadlock_counter + 1 ;
|
|
else
|
|
deadlock_counter = 0;
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
end
|
end
|
if ( CYC_O !== 0 && CYC_O_previous !== 0)
|
if ( CYC_O !== 0 && CYC_O_previous !== 0)
|
begin
|
begin
|
$display("wb_transaction_progress_monitor task waited for 1000 cycles for previous transaction to complete! Time %t ", $time) ;
|
$display("wb_transaction_progress_monitor task waited for 1000 cycles for previous transaction to complete! Time %t ", $time) ;
|
| Line 8958... |
Line 9021... |
begin:wait_start
|
begin:wait_start
|
deadlock_counter = 0 ;
|
deadlock_counter = 0 ;
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
while ( (CYC_O !== 0) && (deadlock_counter < deadlock_max_val) )
|
while ( (CYC_O !== 0) && (deadlock_counter < deadlock_max_val) )
|
begin
|
begin
|
|
if ((!STB_O) || (!ACK_I && !RTY_I && !ERR_I))
|
deadlock_counter = deadlock_counter + 1 ;
|
deadlock_counter = deadlock_counter + 1 ;
|
|
else
|
|
deadlock_counter = 0;
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
end
|
end
|
if ( CYC_O !== 0 )
|
if ( CYC_O !== 0 )
|
begin
|
begin
|
$display("wb_transaction_progress_monitor task waited for 1000 cycles for previous transaction to complete! Time %t ", $time) ;
|
$display("wb_transaction_progress_monitor task waited for 1000 cycles for previous transaction to complete! Time %t ", $time) ;
|
| Line 11389... |
Line 11455... |
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
|
|
|
@(posedge pci_clock) ;
|
|
@(posedge pci_clock) ;
|
|
@(posedge wb_clock) ;
|
|
@(posedge wb_clock) ;
|
|
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
addr_offset = 12'h004 ;
|
addr_offset = 12'h004 ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
ok = 1 ;
|
ok = 1 ;
|
if ( read_data[27] !== 1 )
|
if ( read_data[27] !== 1 )
|
| Line 11490... |
Line 11561... |
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
|
|
|
@(posedge pci_clock) ;
|
|
@(posedge pci_clock) ;
|
|
@(posedge wb_clock) ;
|
|
@(posedge wb_clock) ;
|
|
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
addr_offset = 12'h004 ;
|
addr_offset = 12'h004 ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
ok = 1 ;
|
ok = 1 ;
|
if ( read_data[27] !== 1 )
|
if ( read_data[27] !== 1 )
|
| Line 11595... |
Line 11671... |
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
|
|
|
@(posedge pci_clock) ;
|
|
@(posedge pci_clock) ;
|
|
@(posedge wb_clock) ;
|
|
@(posedge wb_clock) ;
|
|
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
addr_offset = 12'h004 ;
|
addr_offset = 12'h004 ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
ok = 1 ;
|
ok = 1 ;
|
if ( read_data[27] !== 1 )
|
if ( read_data[27] !== 1 )
|
| Line 11703... |
Line 11784... |
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
|
|
|
@(posedge pci_clock) ;
|
|
@(posedge pci_clock) ;
|
|
@(posedge wb_clock) ;
|
|
@(posedge wb_clock) ;
|
|
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
addr_offset = 12'h004 ;
|
addr_offset = 12'h004 ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
ok = 1 ;
|
ok = 1 ;
|
if ( read_data[27] !== 1 )
|
if ( read_data[27] !== 1 )
|
| Line 11811... |
Line 11897... |
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
|
|
|
@(posedge pci_clock) ;
|
|
@(posedge pci_clock) ;
|
|
@(posedge wb_clock) ;
|
|
@(posedge wb_clock) ;
|
|
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
addr_offset = 12'h004 ;
|
addr_offset = 12'h004 ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
ok = 1 ;
|
ok = 1 ;
|
if ( read_data[27] !== 1 )
|
if ( read_data[27] !== 1 )
|
| Line 11917... |
Line 12008... |
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
|
|
|
@(posedge pci_clock) ;
|
|
@(posedge pci_clock) ;
|
|
@(posedge wb_clock) ;
|
|
@(posedge wb_clock) ;
|
|
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
addr_offset = 12'h004 ;
|
addr_offset = 12'h004 ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
ok = 1 ;
|
ok = 1 ;
|
if ( read_data[27] !== 1 )
|
if ( read_data[27] !== 1 )
|
| Line 12023... |
Line 12119... |
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
|
|
|
@(posedge pci_clock) ;
|
|
@(posedge pci_clock) ;
|
|
@(posedge wb_clock) ;
|
|
@(posedge wb_clock) ;
|
|
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
addr_offset = 12'h004 ;
|
addr_offset = 12'h004 ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
ok = 1 ;
|
ok = 1 ;
|
if ( read_data[27] !== 1 )
|
if ( read_data[27] !== 1 )
|
| Line 12129... |
Line 12230... |
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
|
|
|
@(posedge pci_clock) ;
|
|
@(posedge pci_clock) ;
|
|
@(posedge wb_clock) ;
|
|
@(posedge wb_clock) ;
|
|
|
wishbone_slave.cycle_response(3'b100, tb_subseq_waits, 8'h0);
|
wishbone_slave.cycle_response(3'b100, tb_subseq_waits, 8'h0);
|
|
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
addr_offset = 12'h004 ;
|
addr_offset = 12'h004 ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
| Line 12460... |
Line 12566... |
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
|
|
|
@(posedge pci_clock) ;
|
|
@(posedge pci_clock) ;
|
|
@(posedge wb_clock) ;
|
|
@(posedge wb_clock) ;
|
|
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
test_name = "PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT" ;
|
addr_offset = 12'h004 ;
|
addr_offset = 12'h004 ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
config_read(addr_offset, 4'hF, read_data) ;
|
ok = 1 ;
|
ok = 1 ;
|
if ( read_data[27] !== 1 )
|
if ( read_data[27] !== 1 )
|
| Line 14083... |
Line 14194... |
pci_transaction_progress_monitor(Target_Base_Addr_R[target_mem_image], `BC_MEM_READ_LN, 4, 0, 1'b1, 1'b0, 1, ok) ;
|
pci_transaction_progress_monitor(Target_Base_Addr_R[target_mem_image], `BC_MEM_READ_LN, 4, 0, 1'b1, 1'b0, 1, ok) ;
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
test_fail("unexpected transaction was detected on PCI when FastB2B read was repeated") ;
|
test_fail("unexpected transaction was detected on PCI when FastB2B read was repeated") ;
|
end
|
end
|
end
|
end
|
|
begin
|
|
wb_transaction_progress_monitor(Target_Base_Addr_R[target_mem_image], 1'b1, `PCIW_DEPTH - 2, 1'b1, ok) ;
|
|
if ( ok !== 1 )
|
|
test_fail("WISHBONE master did invalid transaction or none at all on WISHBONE bus") ;
|
|
end
|
join
|
join
|
end
|
end
|
disable monitor_error_event3 ;
|
disable monitor_error_event3 ;
|
end
|
end
|
begin:monitor_error_event3
|
begin:monitor_error_event3
|
| Line 15768... |
Line 15884... |
end
|
end
|
|
|
in_use = 1 ;
|
in_use = 1 ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
|
repeat(4)
|
|
@(posedge wb_clock) ;
|
read_flags = 0 ;
|
read_flags = 0 ;
|
read_flags`INIT_WAITS = tb_init_waits ;
|
read_flags`INIT_WAITS = tb_init_waits ;
|
read_flags`SUBSEQ_WAITS = tb_subseq_waits ;
|
read_flags`SUBSEQ_WAITS = tb_subseq_waits ;
|
read_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
read_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
|
|
| Line 15789... |
Line 15909... |
#20 $stop ;
|
#20 $stop ;
|
end
|
end
|
data = read_status`READ_DATA ;
|
data = read_status`READ_DATA ;
|
`else
|
`else
|
`ifdef GUEST
|
`ifdef GUEST
|
|
repeat(4)
|
|
@(posedge wb_clock) ;
|
|
repeat(4)
|
|
@(posedge pci_clock) ;
|
master_check_data_prev = master2_check_received_data ;
|
master_check_data_prev = master2_check_received_data ;
|
master2_check_received_data = 0 ;
|
master2_check_received_data = 0 ;
|
|
|
byte_enables_l = ~byte_enable ;
|
byte_enables_l = ~byte_enable ;
|
pci_address = Target_Base_Addr_R[0] | { 20'h0, offset } ;
|
pci_address = Target_Base_Addr_R[0] | { 20'h0, offset } ;
|
