| Line 4035... |
Line 4035... |
end
|
end
|
begin:wait_perr1
|
begin:wait_perr1
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( PERR === 1 )
|
while ( PERR !== 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( PERR === 0 )
|
|
perr_asserted = 1 ;
|
perr_asserted = 1 ;
|
|
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
|
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
test_fail("bridge failed to process single memory write correctly, or target didn't respond to it") ;
|
test_fail("bridge failed to process single memory write correctly, or target didn't respond to it") ;
|
|
|
repeat(3)
|
repeat(2)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !perr_asserted )
|
disable wait_perr1 ;
|
disable wait_perr1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( perr_asserted && ok )
|
if ( perr_asserted && ok )
|
| Line 4128... |
Line 4129... |
end
|
end
|
begin:wait_perr2
|
begin:wait_perr2
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( PERR === 1 )
|
while ( PERR !== 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( PERR === 0 )
|
|
perr_asserted = 1 ;
|
perr_asserted = 1 ;
|
|
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
|
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
test_fail("bridge failed to process single memory write correctly, or target didn't respond to it") ;
|
test_fail("bridge failed to process single memory write correctly, or target didn't respond to it") ;
|
|
|
repeat(3)
|
repeat(2)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if (!perr_asserted)
|
disable wait_perr2 ;
|
disable wait_perr2 ;
|
end
|
end
|
join
|
join
|
|
|
if ( perr_asserted && ok )
|
if ( perr_asserted && ok )
|
| Line 4287... |
Line 4289... |
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
|
end
|
end
|
begin:wait_perr4
|
begin:wait_perr4
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
while ( PERR === 1 )
|
while ( PERR !== 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( PERR === 0 )
|
|
perr_asserted = 1 ;
|
perr_asserted = 1 ;
|
|
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( target_address, `BC_MEM_READ, 1, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( target_address, `BC_MEM_READ, 1, 0, 1'b1, 1'b0, 0, ok ) ;
|
| Line 4303... |
Line 4304... |
test_fail("bridge failed to process single memory read correctly, or target didn't respond to it") ;
|
test_fail("bridge failed to process single memory read correctly, or target didn't respond to it") ;
|
|
|
repeat(2)
|
repeat(2)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !perr_asserted )
|
disable wait_perr4 ;
|
disable wait_perr4 ;
|
end
|
end
|
join
|
join
|
|
|
if ( read_status`CYC_ACTUAL_TRANSFER !== 1 )
|
if ( read_status`CYC_ACTUAL_TRANSFER !== 1 )
|
| Line 4493... |
Line 4496... |
|
|
// perr can be asserted on idle or next PCI address phase
|
// perr can be asserted on idle or next PCI address phase
|
repeat(2)
|
repeat(2)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !perr_asserted )
|
disable wait_perr5 ;
|
disable wait_perr5 ;
|
end
|
end
|
join
|
join
|
|
|
if ( read_status`CYC_ACTUAL_TRANSFER !== 1 )
|
if ( read_status`CYC_ACTUAL_TRANSFER !== 1 )
|
| Line 4630... |
Line 4635... |
test_fail("bridge failed to start expected read transaction on PCI bus") ;
|
test_fail("bridge failed to start expected read transaction on PCI bus") ;
|
|
|
repeat(2)
|
repeat(2)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !perr_asserted )
|
disable wait_perr6 ;
|
disable wait_perr6 ;
|
end
|
end
|
join
|
join
|
|
|
if ( read_status`CYC_ACTUAL_TRANSFER !== 1 )
|
if ( read_status`CYC_ACTUAL_TRANSFER !== 1 )
|
| Line 4731... |
Line 4738... |
begin
|
begin
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
test_fail("behavioral master failed to start expected transaction or behavioral target didn't respond") ;
|
test_fail("behavioral master failed to start expected transaction or behavioral target didn't respond") ;
|
|
|
|
if ( !perr_asserted )
|
disable wait_serr7 ;
|
disable wait_serr7 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok && !perr_asserted)
|
if ( ok && !perr_asserted)
|
| Line 4786... |
Line 4794... |
32'h1234_5678, // data
|
32'h1234_5678, // data
|
1'b1, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on first phase of dual address
|
1'b0, // make address parity error on second phase of dual address
|
1'b0, // make address parity error on second phase of dual address
|
ok // result of operation
|
ok // result of operation
|
) ;
|
) ;
|
|
if ( !perr_asserted )
|
disable wait_serr8 ;
|
disable wait_serr8 ;
|
end
|
end
|
begin:wait_serr8
|
begin:wait_serr8
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
| Line 4819... |
Line 4828... |
32'h1234_5678, // data
|
32'h1234_5678, // data
|
1'b0, // make address parity error on first phase of dual address
|
1'b0, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
ok // result of operation
|
ok // result of operation
|
) ;
|
) ;
|
|
if ( !perr_asserted )
|
disable wait_serr9 ;
|
disable wait_serr9 ;
|
end
|
end
|
begin:wait_serr9
|
begin:wait_serr9
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
| Line 4886... |
Line 4896... |
32'h1234_5678, // data
|
32'h1234_5678, // data
|
1'b1, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
ok // result of operation
|
ok // result of operation
|
) ;
|
) ;
|
|
if ( !perr_asserted )
|
disable wait_serr10 ;
|
disable wait_serr10 ;
|
end
|
end
|
begin:wait_serr10
|
begin:wait_serr10
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
| Line 5009... |
Line 5020... |
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
end
|
end
|
begin:wait_serr11
|
begin:wait_serr11
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
while( SERR === 1 )
|
while( SERR !== 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( SERR === 0 )
|
|
perr_asserted = 1 ;
|
perr_asserted = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
test_fail("behavioral PCI Master failed to start expected transaction or behavioral PCI target failed to respond to it") ;
|
test_fail("behavioral PCI Master failed to start expected transaction or behavioral PCI target failed to respond to it") ;
|
|
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
#2 ;
|
#1 ;
|
|
if ( !perr_asserted )
|
disable wait_serr11 ;
|
disable wait_serr11 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok && perr_asserted)
|
if ( ok && perr_asserted)
|
| Line 5151... |
Line 5162... |
32'h1234_5678, // data
|
32'h1234_5678, // data
|
1'b1, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on first phase of dual address
|
1'b0, // make address parity error on second phase of dual address
|
1'b0, // make address parity error on second phase of dual address
|
ok // result of operation
|
ok // result of operation
|
) ;
|
) ;
|
|
if ( !perr_asserted )
|
disable wait_serr14 ;
|
disable wait_serr14 ;
|
end
|
end
|
begin:wait_serr14
|
begin:wait_serr14
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
while( SERR === 1 )
|
while( SERR !== 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( SERR === 0 )
|
|
perr_asserted = 1 ;
|
perr_asserted = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok && perr_asserted)
|
if ( ok && perr_asserted)
|
| Line 5289... |
Line 5300... |
32'h1234_5678, // data
|
32'h1234_5678, // data
|
1'b0, // make address parity error on first phase of dual address
|
1'b0, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
ok // result of operation
|
ok // result of operation
|
) ;
|
) ;
|
|
if ( !perr_asserted )
|
disable wait_serr15 ;
|
disable wait_serr15 ;
|
end
|
end
|
begin:wait_serr15
|
begin:wait_serr15
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
while( SERR === 1 )
|
while( SERR !== 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( SERR === 0 )
|
|
perr_asserted = 1 ;
|
perr_asserted = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok && perr_asserted)
|
if ( ok && perr_asserted)
|
| Line 5427... |
Line 5438... |
32'h1234_5678, // data
|
32'h1234_5678, // data
|
1'b1, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
ok // result of operation
|
ok // result of operation
|
) ;
|
) ;
|
|
if ( !perr_asserted )
|
disable wait_serr16 ;
|
disable wait_serr16 ;
|
end
|
end
|
begin:wait_serr16
|
begin:wait_serr16
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
while( SERR === 1 )
|
while( SERR !== 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( SERR === 0 )
|
|
perr_asserted = 1 ;
|
perr_asserted = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok && perr_asserted)
|
if ( ok && perr_asserted)
|
| Line 5578... |
Line 5589... |
begin
|
begin
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
test_fail("behavioral PCI Master failed to start expected transaction or behavioral PCI target failed to respond to it") ;
|
test_fail("behavioral PCI Master failed to start expected transaction or behavioral PCI target failed to respond to it") ;
|
|
|
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !perr_asserted )
|
disable wait_serr12 ;
|
disable wait_serr12 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok && !perr_asserted )
|
if ( ok && !perr_asserted )
|
| Line 5691... |
Line 5705... |
32'h1234_5678, // data
|
32'h1234_5678, // data
|
1'b1, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on first phase of dual address
|
1'b0, // make address parity error on second phase of dual address
|
1'b0, // make address parity error on second phase of dual address
|
ok // result of operation
|
ok // result of operation
|
) ;
|
) ;
|
|
if ( !perr_asserted )
|
disable wait_serr17 ;
|
disable wait_serr17 ;
|
end
|
end
|
begin:wait_serr17
|
begin:wait_serr17
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
| Line 5724... |
Line 5739... |
32'h1234_5678, // data
|
32'h1234_5678, // data
|
1'b0, // make address parity error on first phase of dual address
|
1'b0, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
ok // result of operation
|
ok // result of operation
|
) ;
|
) ;
|
|
if ( !perr_asserted )
|
disable wait_serr18 ;
|
disable wait_serr18 ;
|
end
|
end
|
begin:wait_serr18
|
begin:wait_serr18
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
| Line 5791... |
Line 5807... |
32'h1234_5678, // data
|
32'h1234_5678, // data
|
1'b1, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on first phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
1'b1, // make address parity error on second phase of dual address
|
ok // result of operation
|
ok // result of operation
|
) ;
|
) ;
|
|
if ( !perr_asserted )
|
disable wait_serr19 ;
|
disable wait_serr19 ;
|
end
|
end
|
begin:wait_serr19
|
begin:wait_serr19
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
| Line 5903... |
Line 5920... |
begin
|
begin
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
pci_transaction_progress_monitor(target_address, `BC_MEM_WRITE, 1, 0, 1'b1, 1'b0, 0, ok) ;
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
test_fail("behavioral PCI Master failed to start expected transaction or behavioral PCI target failed to respond to it") ;
|
test_fail("behavioral PCI Master failed to start expected transaction or behavioral PCI target failed to respond to it") ;
|
|
|
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !perr_asserted )
|
disable wait_serr13 ;
|
disable wait_serr13 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok && !perr_asserted )
|
if ( ok && !perr_asserted )
|
| Line 6049... |
Line 6069... |
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
end
|
end
|
begin:wait_perr11
|
begin:wait_perr11
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
while ( PERR === 1 )
|
while ( PERR !== 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( PERR === 0 )
|
|
perr_asserted = 1 ;
|
perr_asserted = 1 ;
|
|
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor(target_address, ((target_mem_image === 1) ? `BC_MEM_WRITE : `BC_IO_WRITE) , 1, 0, 1'b1, 1'b0, 0, ok) ;
|
pci_transaction_progress_monitor(target_address, ((target_mem_image === 1) ? `BC_MEM_WRITE : `BC_IO_WRITE) , 1, 0, 1'b1, 1'b0, 0, ok) ;
|
| Line 6065... |
Line 6084... |
test_fail("behavioral PCI Master failed to start expected transaction or behavioral PCI target failed to respond to it") ;
|
test_fail("behavioral PCI Master failed to start expected transaction or behavioral PCI target failed to respond to it") ;
|
|
|
repeat(2)
|
repeat(2)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !perr_asserted )
|
disable wait_perr11 ;
|
disable wait_perr11 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok && perr_asserted )
|
if ( ok && perr_asserted )
|
| Line 6186... |
Line 6207... |
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
end
|
end
|
begin:wait_perr12
|
begin:wait_perr12
|
perr_asserted = 0 ;
|
perr_asserted = 0 ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
while ( PERR === 1 )
|
while ( PERR !== 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
if ( PERR === 0 )
|
|
perr_asserted = 1 ;
|
perr_asserted = 1 ;
|
end
|
end
|
begin
|
begin
|
|
|
wb_transaction_progress_monitor(target_address, 0, 1, 1'b1, ok) ;
|
wb_transaction_progress_monitor(target_address, 0, 1, 1'b1, ok) ;
|
| Line 6226... |
Line 6246... |
pci_transaction_progress_monitor(target_address, ((target_mem_image === 1) ? `BC_MEM_READ : `BC_IO_READ), 1, 0, 1'b1, 1'b0, 0, ok) ;
|
pci_transaction_progress_monitor(target_address, ((target_mem_image === 1) ? `BC_MEM_READ : `BC_IO_READ), 1, 0, 1'b1, 1'b0, 0, ok) ;
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
test_fail("behavioral PCI master failed to start expected transaction or Bridge's Target failed to respond on it") ;
|
test_fail("behavioral PCI master failed to start expected transaction or Bridge's Target failed to respond on it") ;
|
end
|
end
|
|
|
repeat(3)
|
repeat(2)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !perr_asserted )
|
disable wait_perr12 ;
|
disable wait_perr12 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok && perr_asserted )
|
if ( ok && perr_asserted )
|
| Line 7898... |
Line 7920... |
|
|
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
|
|
end
|
end
|
begin:error_monitor_1
|
begin:error_monitor_1
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_progress_monitor( pci_image_base + 12, 1'b1, 1, 1'b1, ok ) ;
|
wb_transaction_progress_monitor( pci_image_base + 12, 1'b1, 1, 1'b1, ok ) ;
|
if ( ok !== 1 )
|
if ( ok !== 1 )
|
begin
|
begin
|
| Line 7927... |
Line 7951... |
$display("Transaction ordering test failed! PCI Master didn't start expected transaction on PCI bus! Time %t ", $time) ;
|
$display("Transaction ordering test failed! PCI Master didn't start expected transaction on PCI bus! Time %t ", $time) ;
|
test_fail("PCI Master didn't perform expected transaction on PCI bus") ;
|
test_fail("PCI Master didn't perform expected transaction on PCI bus") ;
|
end
|
end
|
end
|
end
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable error_monitor_1 ;
|
disable error_monitor_1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 7985... |
Line 8011... |
begin
|
begin
|
$display("Transaction ordering test failed! WB Master didn't start expected transaction on WB bus! Time %t ", $time) ;
|
$display("Transaction ordering test failed! WB Master didn't start expected transaction on WB bus! Time %t ", $time) ;
|
test_fail("WB Master didn't start expected transaction on WB bus") ;
|
test_fail("WB Master didn't start expected transaction on WB bus") ;
|
end
|
end
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable error_monitor_2 ;
|
disable error_monitor_2 ;
|
end
|
end
|
begin:error_monitor_2
|
begin:error_monitor_2
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
test_name = "SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGET" ;
|
test_name = "SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGET" ;
|
|
|
| Line 8039... |
Line 8069... |
|
|
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
|
|
end
|
end
|
begin:error_monitor_3
|
begin:error_monitor_3
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
if ( target_mem_image == 1 )
|
if ( target_mem_image == 1 )
|
wb_transaction_progress_monitor( pci_image_base, 1'b1, 3, 1'b1, ok ) ;
|
wb_transaction_progress_monitor( pci_image_base, 1'b1, 3, 1'b1, ok ) ;
|
else
|
else
|
| Line 8076... |
Line 8108... |
$display("Transaction ordering test failed! PCI Master didn't start expected transaction on PCI bus! Time %t ", $time) ;
|
$display("Transaction ordering test failed! PCI Master didn't start expected transaction on PCI bus! Time %t ", $time) ;
|
test_fail("PCI Master didn't perform expected transaction on PCI bus") ;
|
test_fail("PCI Master didn't perform expected transaction on PCI bus") ;
|
end
|
end
|
end
|
end
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable error_monitor_3 ;
|
disable error_monitor_3 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 8147... |
Line 8181... |
wb_transaction_progress_monitor( pci_image_base, 1'b1, 1, 1'b1, ok ) ;
|
wb_transaction_progress_monitor( pci_image_base, 1'b1, 1, 1'b1, ok ) ;
|
if ( ok )
|
if ( ok )
|
wb_transaction_progress_monitor( pci_image_base + 4, 1'b1, 1, 1'b1, ok ) ;
|
wb_transaction_progress_monitor( pci_image_base + 4, 1'b1, 1, 1'b1, ok ) ;
|
end
|
end
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable error_monitor_4 ;
|
disable error_monitor_4 ;
|
end
|
end
|
begin:error_monitor_4
|
begin:error_monitor_4
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
| Line 10447... |
Line 10484... |
reg [9:0] expect_length_rd ;
|
reg [9:0] expect_length_rd ;
|
reg [9:0] expect_length_rd1 ;
|
reg [9:0] expect_length_rd1 ;
|
reg [9:0] expect_length_rd2 ;
|
reg [9:0] expect_length_rd2 ;
|
reg [3:0] use_rd_cmd ;
|
reg [3:0] use_rd_cmd ;
|
integer i ;
|
integer i ;
|
|
reg error_monitor_done ;
|
begin:main
|
begin:main
|
|
|
// enable ERROR reporting, because error must NOT be reported and address translation if required!
|
// enable ERROR reporting, because error must NOT be reported and address translation if required!
|
$display("Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.");
|
$display("Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.");
|
$display(" - errors will be reported, but they should not occur!");
|
$display(" - errors will be reported, but they should not occur!");
|
| Line 10709... |
Line 10747... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event1 ;
|
disable monitor_error_event1 ;
|
end
|
end
|
begin:monitor_error_event1
|
begin:monitor_error_event1
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
// increasing the starting address for PCI master and for WB transaction monitor
|
// increasing the starting address for PCI master and for WB transaction monitor
|
rd_address = rd_address + (4 * expect_length_rd) ;
|
rd_address = rd_address + (4 * expect_length_rd) ;
|
| Line 10852... |
Line 10894... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event2 ;
|
disable monitor_error_event2 ;
|
end
|
end
|
begin:monitor_error_event2
|
begin:monitor_error_event2
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
| Line 11301... |
Line 11347... |
reg [31:0] rd_data;
|
reg [31:0] rd_data;
|
reg [3:0] rd_be;
|
reg [3:0] rd_be;
|
integer i ;
|
integer i ;
|
reg do_mem_aborts ;
|
reg do_mem_aborts ;
|
reg do_io_aborts ;
|
reg do_io_aborts ;
|
|
reg error_monitor_done ;
|
begin:main
|
begin:main
|
// enable all error reporting mechanisms - during erroneous reads, errors should not be reported
|
// enable all error reporting mechanisms - during erroneous reads, errors should not be reported
|
|
|
if ( target_mem_image !== -1 )
|
if ( target_mem_image !== -1 )
|
begin
|
begin
|
| Line 11445... |
Line 11492... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event1 ;
|
disable monitor_error_event1 ;
|
end
|
end
|
begin:monitor_error_event1
|
begin:monitor_error_event1
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
| Line 11551... |
Line 11602... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event2 ;
|
disable monitor_error_event2 ;
|
end
|
end
|
begin:monitor_error_event2
|
begin:monitor_error_event2
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
| Line 11661... |
Line 11716... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
if ( !error_monitor_done )
|
disable monitor_error_event3 ;
|
disable monitor_error_event3 ;
|
end
|
end
|
begin:monitor_error_event3
|
begin:monitor_error_event3
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
| Line 11770... |
Line 11828... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event4 ;
|
disable monitor_error_event4 ;
|
end
|
end
|
begin:monitor_error_event4
|
begin:monitor_error_event4
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_stop( 1 ) ;
|
wb_transaction_stop( 1 ) ;
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
end
|
end
|
| Line 11883... |
Line 11945... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event5 ;
|
disable monitor_error_event5 ;
|
end
|
end
|
begin:monitor_error_event5
|
begin:monitor_error_event5
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_stop( 3 ) ;
|
wb_transaction_stop( 3 ) ;
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
end
|
end
|
| Line 11994... |
Line 12060... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event6 ;
|
disable monitor_error_event6 ;
|
end
|
end
|
begin:monitor_error_event6
|
begin:monitor_error_event6
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_stop( 3 ) ;
|
wb_transaction_stop( 3 ) ;
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
end
|
end
|
| Line 12105... |
Line 12175... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event7 ;
|
disable monitor_error_event7 ;
|
end
|
end
|
begin:monitor_error_event7
|
begin:monitor_error_event7
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_stop( `PCIR_DEPTH - 2 ) ;
|
wb_transaction_stop( `PCIR_DEPTH - 2 ) ;
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
end
|
end
|
| Line 12216... |
Line 12290... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event8 ;
|
disable monitor_error_event8 ;
|
end
|
end
|
begin:monitor_error_event8
|
begin:monitor_error_event8
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_stop( `PCIR_DEPTH - 2 ) ;
|
wb_transaction_stop( `PCIR_DEPTH - 2 ) ;
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
end
|
end
|
| Line 12329... |
Line 12407... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event9 ;
|
disable monitor_error_event9 ;
|
end
|
end
|
begin:monitor_error_event9
|
begin:monitor_error_event9
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_stop( 3 ) ;
|
wb_transaction_stop( 3 ) ;
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
wishbone_slave.cycle_response(3'b010, tb_subseq_waits, 8'h0);
|
end
|
end
|
| Line 12556... |
Line 12638... |
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
while ( IRDY === 0 )
|
while ( IRDY === 0 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event10 ;
|
disable monitor_error_event10 ;
|
end
|
end
|
begin:monitor_error_event10
|
begin:monitor_error_event10
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
| Line 12658... |
Line 12744... |
reg [11:0] am_offset ;
|
reg [11:0] am_offset ;
|
reg [11:0] ta_offset ;
|
reg [11:0] ta_offset ;
|
reg [31:0] pci_address ;
|
reg [31:0] pci_address ;
|
reg [3:0] byte_enables ;
|
reg [3:0] byte_enables ;
|
reg ok ;
|
reg ok ;
|
|
reg error_monitor_done ;
|
begin:main
|
begin:main
|
pci_ctrl_offset = 12'h4 ;
|
pci_ctrl_offset = 12'h4 ;
|
if (image_num === 0)
|
if (image_num === 0)
|
begin
|
begin
|
ctrl_offset = {4'h1, `P_IMG_CTRL0_ADDR, 2'b00} ;
|
ctrl_offset = {4'h1, `P_IMG_CTRL0_ADDR, 2'b00} ;
|
| Line 12752... |
Line 12839... |
begin
|
begin
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Abort_On) ;
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Abort_On) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event1
|
begin:monitor_error_event1
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event1 ;
|
disable monitor_error_event1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 12774... |
Line 12865... |
begin
|
begin
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Abort_On) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Abort_On) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event2
|
begin:monitor_error_event2
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_READ, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_READ, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event2 ;
|
disable monitor_error_event2 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 12799... |
Line 12894... |
begin
|
begin
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event3
|
begin:monitor_error_event3
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event3 ;
|
disable monitor_error_event3 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 12823... |
Line 12921... |
begin
|
begin
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event4
|
begin:monitor_error_event4
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_READ, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_READ, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event4 ;
|
disable monitor_error_event4 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 12848... |
Line 12950... |
begin
|
begin
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Abort_On) ;
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Abort_On) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event5
|
begin:monitor_error_event5
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event5 ;
|
disable monitor_error_event5 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 12872... |
Line 12978... |
begin
|
begin
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event6
|
begin:monitor_error_event6
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_READ, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_READ, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event6 ;
|
disable monitor_error_event6 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 12895... |
Line 13005... |
begin
|
begin
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event7
|
begin:monitor_error_event7
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_READ, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_READ, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event7 ;
|
disable monitor_error_event7 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 12918... |
Line 13032... |
begin
|
begin
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Abort_On) ;
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Abort_On) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event8
|
begin:monitor_error_event8
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event8 ;
|
disable monitor_error_event8 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 12943... |
Line 13061... |
begin
|
begin
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hA1A2_A3A4, byte_enables, 1, `Test_Target_Abort_On) ;
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hA1A2_A3A4, byte_enables, 1, `Test_Target_Abort_On) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event9
|
begin:monitor_error_event9
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event9 ;
|
disable monitor_error_event9 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 12964... |
Line 13086... |
begin
|
begin
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hA1A2_A3A4, byte_enables, 1, `Test_Target_Abort_On) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hA1A2_A3A4, byte_enables, 1, `Test_Target_Abort_On) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event10
|
begin:monitor_error_event10
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_READ, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_READ, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event10 ;
|
disable monitor_error_event10 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 12988... |
Line 13115... |
begin
|
begin
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event11
|
begin:monitor_error_event11
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event11 ;
|
disable monitor_error_event11 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 13012... |
Line 13143... |
begin
|
begin
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event12
|
begin:monitor_error_event12
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event12 ;
|
disable monitor_error_event12 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 13036... |
Line 13171... |
begin
|
begin
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
PCIU_IO_WRITE( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 2, `Test_Target_Abort_Before) ;
|
do_pause ( 1 ) ;
|
do_pause ( 1 ) ;
|
end
|
end
|
begin:monitor_error_event13
|
begin:monitor_error_event13
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
test_fail("PCI Master or Monitor detected invalid operation on PCI bus") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_address, `BC_IO_WRITE, 0, 0, 1'b1, 1'b0, 0, ok ) ;
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event13 ;
|
disable monitor_error_event13 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
| Line 13120... |
Line 13259... |
reg [3:0] byte_enables ;
|
reg [3:0] byte_enables ;
|
reg ok ;
|
reg ok ;
|
reg pci_ok ;
|
reg pci_ok ;
|
reg wb_ok ;
|
reg wb_ok ;
|
integer i ;
|
integer i ;
|
|
reg error_monitor_done ;
|
begin:main
|
begin:main
|
`ifdef ADDR_TRAN_IMPL
|
`ifdef ADDR_TRAN_IMPL
|
translation = translate_address ;
|
translation = translate_address ;
|
`else
|
`else
|
translation = 0 ;
|
translation = 0 ;
|
| Line 13157... |
Line 13297... |
begin
|
begin
|
wb_transaction_progress_monitor( expect_address, 1'b1, 1, 1'b1, wb_ok ) ;
|
wb_transaction_progress_monitor( expect_address, 1'b1, 1, 1'b1, wb_ok ) ;
|
if ( wb_ok !== 1 )
|
if ( wb_ok !== 1 )
|
test_fail("WISHBONE Master started invalid transaction or none at all on WB bus after single I/O write was posted on PCI") ;
|
test_fail("WISHBONE Master started invalid transaction or none at all on WB bus after single I/O write was posted on PCI") ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_pci_error_1 ;
|
disable monitor_pci_error_1 ;
|
end
|
end
|
begin:monitor_pci_error_1
|
begin:monitor_pci_error_1
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO refernce to Target" ) ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO refernce to Target" ) ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
byte_enables = 4'b1111 ;
|
byte_enables = 4'b1111 ;
|
for ( i = 0 ; i < 4 ; i = i + 1 )
|
for ( i = 0 ; i < 4 ; i = i + 1 )
|
| Line 13183... |
Line 13327... |
begin
|
begin
|
wb_transaction_progress_monitor( expect_address, 1'b1, 1, 1'b1, wb_ok ) ;
|
wb_transaction_progress_monitor( expect_address, 1'b1, 1, 1'b1, wb_ok ) ;
|
if ( wb_ok !== 1 )
|
if ( wb_ok !== 1 )
|
test_fail("WISHBONE Master started invalid transaction or none at all on WB bus after single I/O write was posted on PCI") ;
|
test_fail("WISHBONE Master started invalid transaction or none at all on WB bus after single I/O write was posted on PCI") ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_pci_error_2 ;
|
disable monitor_pci_error_2 ;
|
end
|
end
|
begin:monitor_pci_error_2
|
begin:monitor_pci_error_2
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO reference to Target" ) ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO reference to Target" ) ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( !pci_ok || !wb_ok )
|
if ( !pci_ok || !wb_ok )
|
disable loop_1 ;
|
disable loop_1 ;
|
| Line 13223... |
Line 13371... |
|
|
do_pause ( 2 ) ;
|
do_pause ( 2 ) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Normal_Completion) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Normal_Completion) ;
|
do_pause ( 16 ) ;
|
do_pause ( 16 ) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_pci_error_3 ;
|
disable monitor_pci_error_3 ;
|
end
|
end
|
begin:monitor_pci_error_3
|
begin:monitor_pci_error_3
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO read reference to Target" ) ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO read reference to Target" ) ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( !pci_ok || !wb_ok )
|
if ( !pci_ok || !wb_ok )
|
begin
|
begin
|
| Line 13257... |
Line 13409... |
|
|
do_pause ( 2 ) ;
|
do_pause ( 2 ) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Normal_Completion) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Normal_Completion) ;
|
do_pause ( 16 ) ;
|
do_pause ( 16 ) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_pci_error_4 ;
|
disable monitor_pci_error_4 ;
|
end
|
end
|
begin:monitor_pci_error_4
|
begin:monitor_pci_error_4
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO read reference to Target" ) ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO read reference to Target" ) ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( !pci_ok || !wb_ok )
|
if ( !pci_ok || !wb_ok )
|
begin
|
begin
|
| Line 13291... |
Line 13447... |
|
|
do_pause ( 2 ) ;
|
do_pause ( 2 ) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Normal_Completion) ;
|
PCIU_IO_READ( `Test_Master_1, pci_address, 32'hAAAA_AAAA, byte_enables, 1, `Test_Target_Normal_Completion) ;
|
do_pause ( 16 ) ;
|
do_pause ( 16 ) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_pci_error_5 ;
|
disable monitor_pci_error_5 ;
|
end
|
end
|
begin:monitor_pci_error_5
|
begin:monitor_pci_error_5
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO read reference to Target" ) ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO read reference to Target" ) ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( pci_ok && wb_ok )
|
if ( pci_ok && wb_ok )
|
test_ok ;
|
test_ok ;
|
| Line 13323... |
Line 13483... |
reg ok ;
|
reg ok ;
|
reg pci_ok ;
|
reg pci_ok ;
|
reg wb_ok ;
|
reg wb_ok ;
|
integer i ;
|
integer i ;
|
reg [11:0] offset ;
|
reg [11:0] offset ;
|
|
reg error_monitor_done ;
|
begin:main
|
begin:main
|
`ifdef ADDR_TRAN_IMPL
|
`ifdef ADDR_TRAN_IMPL
|
translation = translate_address ;
|
translation = translate_address ;
|
`else
|
`else
|
translation = 0 ;
|
translation = 0 ;
|
| Line 13409... |
Line 13570... |
begin
|
begin
|
wb_transaction_progress_monitor( expect_address, 1'b1, 0, 1'b1, wb_ok ) ;
|
wb_transaction_progress_monitor( expect_address, 1'b1, 0, 1'b1, wb_ok ) ;
|
if ( wb_ok !== 1 )
|
if ( wb_ok !== 1 )
|
test_fail("WISHBONE Master started invalid transaction or none at all on WB bus after single I/O write was posted on PCI") ;
|
test_fail("WISHBONE Master started invalid transaction or none at all on WB bus after single I/O write was posted on PCI") ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_pci_error_2 ;
|
disable monitor_pci_error_2 ;
|
end
|
end
|
begin:monitor_pci_error_2
|
begin:monitor_pci_error_2
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO reference to Target" ) ;
|
test_fail ( "PCI Monitor or PCI Master detected an error on PCI bus while doing IO reference to Target" ) ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
test_name = "INTERRUPT REQUEST ASSERTION AFTER ERROR TERMINATED WRITE ON WISHBONE" ;
|
test_name = "INTERRUPT REQUEST ASSERTION AFTER ERROR TERMINATED WRITE ON WISHBONE" ;
|
`ifdef HOST
|
`ifdef HOST
|
| Line 14487... |
Line 14652... |
reg [3:0] byte_enables ;
|
reg [3:0] byte_enables ;
|
reg [9:0] expect_length ;
|
reg [9:0] expect_length ;
|
|
|
reg do_mem_disconnects ;
|
reg do_mem_disconnects ;
|
reg do_io_disconnects ;
|
reg do_io_disconnects ;
|
|
reg error_monitor_done ;
|
begin:main
|
begin:main
|
if ( target_mem_image !== -1 )
|
if ( target_mem_image !== -1 )
|
begin
|
begin
|
do_mem_disconnects = 1 ;
|
do_mem_disconnects = 1 ;
|
|
|
| Line 14577... |
Line 14743... |
`Test_Target_Retry_Before, `Test_Expect_No_Master_Abort);
|
`Test_Target_Retry_Before, `Test_Expect_No_Master_Abort);
|
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event1 ;
|
disable monitor_error_event1 ;
|
end
|
end
|
begin:monitor_error_event1
|
begin:monitor_error_event1
|
|
error_monitor_done = 0 ;
|
ok = 1 ;
|
ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on bursts to configuration space") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on bursts to configuration space") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
config_read(pci_address, 4'hF, data) ;
|
config_read(pci_address, 4'hF, data) ;
|
if ( data [15:0] !== 16'h04_04 )
|
if ( data [15:0] !== 16'h04_04 )
|
| Line 14621... |
Line 14791... |
|
|
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event2 ;
|
disable monitor_error_event2 ;
|
end
|
end
|
begin:monitor_error_event2
|
begin:monitor_error_event2
|
|
error_monitor_done = 0 ;
|
ok = 1 ;
|
ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on bursts to configuration space") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on bursts to configuration space") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
config_read(pci_address, 4'hF, data) ;
|
config_read(pci_address, 4'hF, data) ;
|
if ( data [15:0] !== 16'h04_04 )
|
if ( data [15:0] !== 16'h04_04 )
|
| Line 14671... |
Line 14845... |
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
if ( !error_monitor_done )
|
disable monitor_error_event3 ;
|
disable monitor_error_event3 ;
|
end
|
end
|
begin:monitor_error_event3
|
begin:monitor_error_event3
|
|
error_monitor_done = 0 ;
|
ok = 1 ;
|
ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on bursts to configuration space") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on bursts to configuration space") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
| Line 14708... |
Line 14885... |
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event4 ;
|
disable monitor_error_event4 ;
|
end
|
end
|
begin:monitor_error_event4
|
begin:monitor_error_event4
|
|
error_monitor_done = 0 ;
|
ok = 1 ;
|
ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on bursts to configuration space") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on bursts to configuration space") ;
|
ok = 0 ;
|
ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok )
|
if ( ok )
|
test_ok ;
|
test_ok ;
|
| Line 14799... |
Line 14980... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event5 ;
|
disable monitor_error_event5 ;
|
end
|
end
|
begin:monitor_error_event5
|
begin:monitor_error_event5
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target write burst to WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target write burst to WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
if ( wb_ok !== 1 )
|
if ( wb_ok !== 1 )
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
| Line 14838... |
Line 15023... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event6 ;
|
disable monitor_error_event6 ;
|
end
|
end
|
begin:monitor_error_event6
|
begin:monitor_error_event6
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target write burst to WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target write burst to WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
if ( wb_ok !== 1 )
|
if ( wb_ok !== 1 )
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
| Line 14893... |
Line 15082... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event7 ;
|
disable monitor_error_event7 ;
|
end
|
end
|
begin:monitor_error_event7
|
begin:monitor_error_event7
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( wb_ok && pci_ok )
|
if ( wb_ok && pci_ok )
|
test_ok ;
|
test_ok ;
|
| Line 14942... |
Line 15135... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event8 ;
|
disable monitor_error_event8 ;
|
end
|
end
|
begin:monitor_error_event8
|
begin:monitor_error_event8
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( wb_ok && pci_ok )
|
if ( wb_ok && pci_ok )
|
test_ok ;
|
test_ok ;
|
| Line 14975... |
Line 15172... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event9 ;
|
disable monitor_error_event9 ;
|
end
|
end
|
begin:monitor_error_event9
|
begin:monitor_error_event9
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target write burst to WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target write burst to WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
if ( wb_ok !== 1 )
|
if ( wb_ok !== 1 )
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
| Line 15012... |
Line 15213... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event10 ;
|
disable monitor_error_event10 ;
|
end
|
end
|
begin:monitor_error_event10
|
begin:monitor_error_event10
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target write burst to WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target write burst to WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
if ( wb_ok !== 1 )
|
if ( wb_ok !== 1 )
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
| Line 15049... |
Line 15254... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event11 ;
|
disable monitor_error_event11 ;
|
end
|
end
|
begin:monitor_error_event11
|
begin:monitor_error_event11
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target write burst to WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target write burst to WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
if ( wb_ok !== 1 )
|
if ( wb_ok !== 1 )
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
| Line 15104... |
Line 15313... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event12 ;
|
disable monitor_error_event12 ;
|
end
|
end
|
begin:monitor_error_event12
|
begin:monitor_error_event12
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( wb_ok && pci_ok )
|
if ( wb_ok && pci_ok )
|
test_ok ;
|
test_ok ;
|
| Line 15151... |
Line 15364... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event13 ;
|
disable monitor_error_event13 ;
|
end
|
end
|
begin:monitor_error_event13
|
begin:monitor_error_event13
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( wb_ok && pci_ok )
|
if ( wb_ok && pci_ok )
|
test_ok ;
|
test_ok ;
|
| Line 15198... |
Line 15415... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event14 ;
|
disable monitor_error_event14 ;
|
end
|
end
|
begin:monitor_error_event14
|
begin:monitor_error_event14
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( wb_ok && pci_ok )
|
if ( wb_ok && pci_ok )
|
test_ok ;
|
test_ok ;
|
| Line 15335... |
Line 15556... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event15 ;
|
disable monitor_error_event15 ;
|
end
|
end
|
begin:monitor_error_event15
|
begin:monitor_error_event15
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target IO burst write") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target IO burst write") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
if ( wb_ok !== 1 )
|
if ( wb_ok !== 1 )
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
| Line 15371... |
Line 15596... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event16 ;
|
disable monitor_error_event16 ;
|
end
|
end
|
begin:monitor_error_event16
|
begin:monitor_error_event16
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target IO burst write") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target IO burst write") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
wb_transaction_progress_monitor(pci_address, 1'b1, expect_length, 1'b1, wb_ok) ;
|
if ( wb_ok !== 1 )
|
if ( wb_ok !== 1 )
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
test_fail("WISHBONE Master started invalid transaction or none at all on WISHBONE bus") ;
|
| Line 15429... |
Line 15658... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event17 ;
|
disable monitor_error_event17 ;
|
end
|
end
|
begin:monitor_error_event17
|
begin:monitor_error_event17
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( wb_ok && pci_ok )
|
if ( wb_ok && pci_ok )
|
test_ok ;
|
test_ok ;
|
| Line 15478... |
Line 15711... |
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable monitor_error_event18 ;
|
disable monitor_error_event18 ;
|
end
|
end
|
begin:monitor_error_event18
|
begin:monitor_error_event18
|
|
error_monitor_done = 0 ;
|
pci_ok = 1 ;
|
pci_ok = 1 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
test_fail("PCI Master or Monitor signaled an error while testing disconnect on Target read burst from WISHBONE") ;
|
pci_ok = 0 ;
|
pci_ok = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( wb_ok && pci_ok )
|
if ( wb_ok && pci_ok )
|
test_ok ;
|
test_ok ;
|
| Line 15800... |
Line 16037... |
PCIU_IO_READ( `Test_Master_1, pci_image_base, 32'h1234_5678, 4'h0, 1, `Test_Target_Retry_On ) ;
|
PCIU_IO_READ( `Test_Master_1, pci_image_base, 32'h1234_5678, 4'h0, 1, `Test_Target_Retry_On ) ;
|
|
|
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
end
|
end
|
begin:error_monitor1
|
begin:error_monitor1
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
ok_pci = 0 ;
|
ok_pci = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
if ( test_mem )
|
if ( test_mem )
|
wb_transaction_progress_monitor( pci_image_base, 1'b0, 4, 1'b1, ok_wb ) ;
|
wb_transaction_progress_monitor( pci_image_base, 1'b0, 4, 1'b1, ok_wb ) ;
|
else
|
else
|
| Line 15816... |
Line 16055... |
begin
|
begin
|
test_fail("Bridge failed to process Target Memory read correctly") ;
|
test_fail("Bridge failed to process Target Memory read correctly") ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
if ( ok_pci )
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable error_monitor1 ;
|
disable error_monitor1 ;
|
end
|
end
|
join
|
join
|
|
|
clocks_after_completion = 0 ;
|
clocks_after_completion = 0 ;
|
| Line 15852... |
Line 16092... |
PCIU_IO_READ( `Test_Master_1, pci_image_base + 4, 32'h1234_5678, 4'h0, 1, `Test_Target_Retry_On ) ;
|
PCIU_IO_READ( `Test_Master_1, pci_image_base + 4, 32'h1234_5678, 4'h0, 1, `Test_Target_Retry_On ) ;
|
|
|
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
end
|
end
|
begin:error_monitor2
|
begin:error_monitor2
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
ok_pci = 0 ;
|
ok_pci = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
begin
|
begin
|
wait ( clocks_after_completion === 32'h0000_FFF0 ) ;
|
wait ( clocks_after_completion === 32'h0000_FFF0 ) ;
|
repeat( 'hFF )
|
repeat( 'hFF )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
| Line 15889... |
Line 16131... |
|
|
do_pause(1) ;
|
do_pause(1) ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_image_base + 4, test_mem ? `BC_MEM_READ : `BC_IO_READ, test_mem ? 4 : 1, 0, 1'b1, 1'b0, 0, ok ) ;
|
pci_transaction_progress_monitor( pci_image_base + 4, test_mem ? `BC_MEM_READ : `BC_IO_READ, test_mem ? 4 : 1, 0, 1'b1, 1'b0, 0, ok ) ;
|
if ( ok_pci )
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable error_monitor2 ;
|
disable error_monitor2 ;
|
end
|
end
|
join
|
join
|
end
|
end
|
join
|
join
|
| Line 16011... |
Line 16254... |
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
|
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
|
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
|
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
if ( ok_pci )
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable error_monitor3 ;
|
disable error_monitor3 ;
|
end
|
end
|
begin:error_monitor3
|
begin:error_monitor3
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
ok_pci = 0 ;
|
ok_pci = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok_wb && ok_pci )
|
if ( ok_wb && ok_pci )
|
begin
|
begin
|
| Line 16150... |
Line 16396... |
else
|
else
|
PCIU_IO_READ( `Test_Master_1, pci_image_base, 32'h8765_4321, 4'h0, 1, `Test_Target_Normal_Completion ) ;
|
PCIU_IO_READ( `Test_Master_1, pci_image_base, 32'h8765_4321, 4'h0, 1, `Test_Target_Normal_Completion ) ;
|
|
|
do_pause(1) ;
|
do_pause(1) ;
|
|
|
if ( ok_pci )
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable error_monitor4 ;
|
disable error_monitor4 ;
|
end
|
end
|
begin:error_monitor4
|
begin:error_monitor4
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
ok_pci = 0 ;
|
ok_pci = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok_wb && ok_pci )
|
if ( ok_wb && ok_pci )
|
test_ok ;
|
test_ok ;
|
| Line 16226... |
Line 16475... |
disable main ;
|
disable main ;
|
end
|
end
|
end
|
end
|
join
|
join
|
|
|
if ( ok_pci )
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable error_monitor5 ;
|
disable error_monitor5 ;
|
end
|
end
|
begin:error_monitor5
|
begin:error_monitor5
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
ok_pci = 0 ;
|
ok_pci = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
if ( ok_wb && ok_pci )
|
if ( ok_wb && ok_pci )
|
test_ok ;
|
test_ok ;
|
| Line 16311... |
Line 16563... |
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
|
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
|
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
|
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
if ( ok_pci )
|
#1 ;
|
|
if ( !error_monitor_done )
|
disable error_monitor6 ;
|
disable error_monitor6 ;
|
end
|
end
|
begin:error_monitor6
|
begin:error_monitor6
|
|
error_monitor_done = 0 ;
|
@(error_event_int) ;
|
@(error_event_int) ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
|
ok_pci = 0 ;
|
ok_pci = 0 ;
|
|
error_monitor_done = 1 ;
|
end
|
end
|
join
|
join
|
|
|
$display("PCIU monitor (WB bus) should NOT complain any more!") ;
|
$display("PCIU monitor (WB bus) should NOT complain any more!") ;
|
$fdisplay(pciu_mon_log_file_desc,
|
$fdisplay(pciu_mon_log_file_desc,
|
