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`include "pci_constants.v"
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`include "pci_constants.v"
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`include "bus_commands.v"
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`include "bus_commands.v"
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`include "pci_testbench_defines.v"
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`include "pci_testbench_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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`ifdef HOST
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`ifdef NO_CNF_IMAGE
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`else
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`define TEST_CONF_CYCLE_TYPE1_REFERENCE
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`endif
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`else
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`define TEST_CONF_CYCLE_TYPE1_REFERENCE
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`endif
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module SYSTEM ;
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module SYSTEM ;
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`include "pci_blue_constants.vh"
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`include "pci_blue_constants.vh"
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`include "pci_blue_options.vh"
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`include "pci_blue_options.vh"
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$display("########################################################################") ;
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$display("########################################################################") ;
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$display("Testing PCI target images' features!") ;
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$display("Testing PCI target images' features!") ;
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configure_bridge_target_base_addresses ;
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configure_bridge_target_base_addresses ;
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`ifdef TEST_CONF_CYCLE_TYPE1_REFERENCE
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test_conf_cycle_type1_reference ;
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`endif
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`ifdef HOST
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`ifdef HOST
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`ifdef NO_CNF_IMAGE
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`ifdef NO_CNF_IMAGE
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`ifdef PCI_IMAGE0
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`ifdef PCI_IMAGE0
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$display("PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!") ;
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$display("PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!") ;
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test_pci_image(0) ;
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test_pci_image(0) ;
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in_use = 0 ;
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in_use = 0 ;
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end //main
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end //main
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endtask // configuration_cycle_read
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endtask // configuration_cycle_read
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`ifdef TEST_CONF_CYCLE_TYPE1_REFERENCE
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task test_conf_cycle_type1_reference ;
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reg [31:0] address ;
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reg in_use ;
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reg master_check_data_prev ;
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reg [31:0] data ;
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reg monitor_ok ;
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reg master_ok ;
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begin:main
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if ( in_use === 1 )
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begin
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$display("test_conf_cycle_type1_reference task re-entered! Time %t ", $time) ;
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disable main ;
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end
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in_use = 1 ;
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master_check_data_prev = master1_check_received_data ;
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test_name = "NO RESPONSE TO CONFIGURATION CYCLE TYPE 1 READ TARGET REFERENCE" ;
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address = `TAR0_IDSEL_ADDR ;
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address[1:0] = 2'b01 ;
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`ifdef HOST
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conf_cyc_type1_target_bus_num = 255 ;
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`endif
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master_ok = 1 ;
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fork
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begin
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PCIU_CONFIG_READ_MASTER_ABORT ("CFG_READ ", `Test_Master_1, address, 4'hE) ;
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do_pause(1) ;
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end
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begin:error_monitor1
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@(error_event_int) ;
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master_ok = 0 ;
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test_fail("PCI Behavioral master signaled an error during the target reference") ;
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end
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begin
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pci_transaction_progress_monitor
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(
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address, // expected address on PCI bus
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`BC_CONF_READ, // expected bus command on PCI bus
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0, // expected number of succesfull data phases
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0, // expected number of cycles the transaction will take on PCI bus
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1'b1, // monitor checking/not checking number of transfers
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1'b0, // monitor checking/not checking number of cycles
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0, // tell to monitor if it has to expect a fast back to back transaction
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monitor_ok // status - 1 success, 0 failure
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) ;
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@(posedge pci_clock);
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#1 ;
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if (master_ok)
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disable error_monitor1 ;
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if (!monitor_ok)
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test_fail("PCI Transaction Monitor detected unexpected transaction on PCI bus") ;
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end
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join
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if (monitor_ok && master_ok)
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test_ok ;
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test_name = "NO RESPONSE TO CONFIGURATION CYCLE TYPE 1 WRITE TARGET REFERENCE" ;
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master_ok = 1 ;
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fork
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begin
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PCIU_CONFIG_WRITE_MASTER_ABORT ("CFG_WRITE ", `Test_Master_1, address, 4'hF) ;
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do_pause(1) ;
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end
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begin:error_monitor2
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@(error_event_int) ;
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master_ok = 0 ;
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test_fail("PCI Behavioral master signaled an error during the target reference") ;
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end
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begin
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pci_transaction_progress_monitor
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(
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address, // expected address on PCI bus
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`BC_CONF_WRITE, // expected bus command on PCI bus
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0, // expected number of succesfull data phases
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0, // expected number of cycles the transaction will take on PCI bus
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1'b1, // monitor checking/not checking number of transfers
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1'b0, // monitor checking/not checking number of cycles
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0, // tell to monitor if it has to expect a fast back to back transaction
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monitor_ok // status - 1 success, 0 failure
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) ;
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@(posedge pci_clock);
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#1 ;
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if (master_ok)
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disable error_monitor2 ;
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if (!monitor_ok)
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test_fail("PCI Transaction Monitor detected unexpected transaction on PCI bus") ;
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end
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join
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master1_check_received_data = master_check_data_prev ;
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if (monitor_ok && master_ok)
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test_ok ;
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in_use = 0 ;
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end //main
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endtask // test_conf_cycle_type1_reference
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`endif
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`ifdef HOST
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`ifdef HOST
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task generate_configuration_cycle ;
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task generate_configuration_cycle ;
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input [7:0] bus_num ;
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input [7:0] bus_num ;
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input [4:0] device_num ;
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input [4:0] device_num ;
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input [2:0] func_num ;
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input [2:0] func_num ;
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// Access a location with no high-order bits set, assuring that no device responds
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// Access a location with no high-order bits set, assuring that no device responds
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task PCIU_CONFIG_READ_MASTER_ABORT;
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task PCIU_CONFIG_READ_MASTER_ABORT;
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input [79:0] name;
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input [79:0] name;
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input [2:0] master_number;
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input [2:0] master_number;
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input [9:0] size;
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input [31:0] address ;
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input [3:0] be ;
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begin
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begin
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DO_REF (name[79:0], master_number[2:0], `NO_DEVICE_IDSEL_ADDR,
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DO_REF (name[79:0], master_number[2:0], address,
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PCI_COMMAND_CONFIG_READ, 32'h76543210, `Test_All_Bytes, size[9:0],
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PCI_COMMAND_CONFIG_READ, 32'h76543210, ~be, 1,
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`Test_Addr_Perr, `Test_Data_Perr, `Test_One_Zero_Master_WS,
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`Test_No_Addr_Perr, `Test_No_Data_Perr, `Test_One_Zero_Master_WS,
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`Test_One_Zero_Target_WS, `Test_Devsel_Medium, `Test_No_Fast_B2B,
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`Test_One_Zero_Target_WS, `Test_Devsel_Medium, `Test_No_Fast_B2B,
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`Test_Target_Normal_Completion, `Test_Expect_Master_Abort);
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`Test_Target_Normal_Completion, `Test_Expect_Master_Abort);
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end
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end
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endtask // PCIU_CONFIG_READ_MASTER_ABORT
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endtask // PCIU_CONFIG_READ_MASTER_ABORT
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// Access a location with no high-order bits set, assuring that no device responds
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// Access a location with no high-order bits set, assuring that no device responds
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task PCIU_CONFIG_WRITE_MASTER_ABORT;
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task PCIU_CONFIG_WRITE_MASTER_ABORT;
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input [79:0] name;
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input [79:0] name;
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input [2:0] master_number;
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input [2:0] master_number;
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input [9:0] size;
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input [31:0] address ;
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input [3:0] be ;
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begin
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begin
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DO_REF (name[79:0], master_number[2:0], `NO_DEVICE_IDSEL_ADDR,
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DO_REF (name[79:0], master_number[2:0], address,
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PCI_COMMAND_CONFIG_WRITE, 32'h76543210, `Test_All_Bytes, size[9:0],
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PCI_COMMAND_CONFIG_WRITE, 32'h76543210, ~be, 1,
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`Test_Addr_Perr, `Test_Data_Perr, `Test_One_Zero_Master_WS,
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`Test_No_Addr_Perr, `Test_No_Data_Perr, `Test_One_Zero_Master_WS,
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`Test_One_Zero_Target_WS, `Test_Devsel_Medium, `Test_No_Fast_B2B,
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`Test_One_Zero_Target_WS, `Test_Devsel_Medium, `Test_No_Fast_B2B,
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`Test_Target_Normal_Completion, `Test_Expect_Master_Abort);
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`Test_Target_Normal_Completion, `Test_Expect_Master_Abort);
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end
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end
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endtask // PCIU_CONFIG_WRITE_MASTER_ABORT
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endtask // PCIU_CONFIG_WRITE_MASTER_ABORT
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