| Line 37... |
Line 37... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/09/25 09:54:47 mihad
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// Added completion expiration test for WB Slave unit. Changed expiration signalling
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//
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// Revision 1.7 2002/08/22 09:20:16 mihad
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// Revision 1.7 2002/08/22 09:20:16 mihad
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// Oops, never before noticed that OC header is missing
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// Oops, never before noticed that OC header is missing
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//
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//
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//
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//
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| Line 133... |
Line 136... |
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wire TAR2_IDSEL = AD[`TAR2_IDSEL_INDEX] ;
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wire TAR2_IDSEL = AD[`TAR2_IDSEL_INDEX] ;
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wire reset_wb ; // reset to Wb devices
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wire reset_wb ; // reset to Wb devices
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`ifdef PCI_BIST
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wire SO ;
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reg SI ;
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reg shift_DR ;
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reg capture_DR ;
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reg extest ;
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reg tck ;
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`endif
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`ifdef GUEST
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`ifdef GUEST
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wire RST = ~reset ;
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wire RST = ~reset ;
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assign reset_wb = RST_O ;
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assign reset_wb = RST_O ;
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`else
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`else
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pullup(RST) ;
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pullup(RST) ;
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| Line 193... |
Line 205... |
.WE_O ( WE_O ),
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.WE_O ( WE_O ),
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.CAB_O ( CAB_O ),
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.CAB_O ( CAB_O ),
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.ACK_I ( ACK_I ),
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.ACK_I ( ACK_I ),
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.RTY_I ( RTY_I ),
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.RTY_I ( RTY_I ),
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.ERR_I ( ERR_I )
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.ERR_I ( ERR_I )
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`ifdef PCI_BIST
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,
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.SO (SO),
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.SI (SI),
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.shift_DR (shift_DR),
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.capture_DR (capture_DR),
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.extest (extest),
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.tck (tck)
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`endif
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) ;
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) ;
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WB_MASTER_BEHAVIORAL wishbone_master
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WB_MASTER_BEHAVIORAL wishbone_master
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(
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(
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.CLK_I(wb_clock),
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.CLK_I(wb_clock),
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| Line 600... |
Line 622... |
integer target_mem_image ;
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integer target_mem_image ;
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integer target_io_image ;
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integer target_io_image ;
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initial
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initial
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begin
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begin
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`ifdef PCI_BIST
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SI = 0 ;
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shift_DR = 0 ;
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capture_DR = 0 ;
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extest = 0 ;
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tck = 0 ;
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`endif
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next_test_name[79:0] <= "Nowhere___";
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next_test_name[79:0] <= "Nowhere___";
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reset = 1'b1 ;
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reset = 1'b1 ;
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pci_clock = 1'b0 ;
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pci_clock = 1'b0 ;
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wb_clock = 1'b1 ;
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wb_clock = 1'b1 ;
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target_message = 32'h0000_0000 ;
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target_message = 32'h0000_0000 ;
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| Line 788... |
Line 818... |
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task run_tests ;
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task run_tests ;
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begin
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begin
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// first - reset logic
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// first - reset logic
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do_reset ;
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do_reset ;
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// if BIST is implemented, give it a go
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`ifdef PCI_BIST
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run_bist_test ;
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`endif
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test_initial_conf_values ;
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test_initial_conf_values ;
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next_test_name[79:0] <= "Initing...";
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next_test_name[79:0] <= "Initing...";
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test_target_response[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1 ;
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test_target_response[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1 ;
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| Line 19011... |
Line 19046... |
`endif
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`endif
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in_use = 0 ;
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in_use = 0 ;
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end
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end
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endtask //config_read
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endtask //config_read
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`ifdef PCI_BIST
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`ifdef WB_RAM_DONT_SHARE
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`ifdef PCI_RAM_DONT_SHARE
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parameter bist_chain_length = 8 ;
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`else
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parameter bist_chain_length = 6 ;
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`endif
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`else
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`ifdef PCI_RAM_DONT_SHARE
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bist_chain_length = 6 ;
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`else
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bist_chain_length = 4 ;
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`endif
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`endif
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task run_bist_test ;
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reg [(bist_chain_length - 1):0] bist_result_vector ;
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integer count ;
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integer deadlock_count ;
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begin
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test_name = "BIST FOR RAMS RUN" ;
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SI = 0 ;
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shift_DR = 0 ;
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capture_DR = 0 ;
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extest = 0 ;
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tck = 0 ;
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fork
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begin
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repeat(2)
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@(posedge wb_clock) ;
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end
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begin
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repeat(2)
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@(posedge pci_clock) ;
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end
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join
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// test is run with forcing extest high
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extest <= 1'b1 ;
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bist_result_vector = 0 ;
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// result vector must be all 1s, because in RTL there cannot be a reason for BIST to fail
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fork
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begin:scan
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while (bist_result_vector !== {bist_chain_length{1'b1}})
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begin
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@(negedge tck) ;
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capture_DR <= #1 1'b1 ;
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@(negedge tck) ;
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capture_DR <= #1 1'b0 ;
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shift_DR <= #1 1'b1 ;
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for (count = 0 ; count < bist_chain_length ; count = count + 1'b1)
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begin
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@(negedge tck) ;
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bist_result_vector[count] = SO ;
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end
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shift_DR <= #1 1'b0 ;
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end
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#1 disable deadlock ;
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@(negedge tck) ;
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extest <= #1 1'b0 ;
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#1 ;
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disable tck_gen ;
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test_ok ;
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end
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begin:deadlock
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for (deadlock_count = 0; deadlock_count <= 100000; deadlock_count = deadlock_count + 1'b1)
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begin
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@(posedge pci_clock) ;
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@(posedge wb_clock) ;
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end
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test_fail("BIST Test didn't finish as expected") ;
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extest <= #1 1'b0 ;
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disable scan ;
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@(negedge tck) ;
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#1 ;
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disable tck_gen ;
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end
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begin:tck_gen
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forever
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#50 tck = !tck ;
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end
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join
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end
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endtask // run_bist_test
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`endif
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task test_fail ;
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task test_fail ;
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input [7999:0] failure_reason ;
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input [7999:0] failure_reason ;
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reg [8007:0] display_failure ;
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reg [8007:0] display_failure ;
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reg [799:0] display_test ;
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reg [799:0] display_test ;
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begin
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begin
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