| Line 37... |
Line 37... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2002/10/11 10:08:57 mihad
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// Added additional testcase and changed rst name in BIST to trst
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//
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// Revision 1.9 2002/10/08 17:17:02 mihad
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// Revision 1.9 2002/10/08 17:17:02 mihad
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// Added BIST signals for RAMs.
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// Added BIST signals for RAMs.
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//
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//
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// Revision 1.8 2002/09/25 09:54:47 mihad
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// Revision 1.8 2002/09/25 09:54:47 mihad
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// Added completion expiration test for WB Slave unit. Changed expiration signalling
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// Added completion expiration test for WB Slave unit. Changed expiration signalling
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| Line 19461... |
Line 19464... |
1, // number of transfers
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1, // number of transfers
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`Test_Target_Retry_On // expected target termination
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`Test_Target_Retry_On // expected target termination
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) ;
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) ;
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end
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end
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do_pause(1) ;
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wb_transaction_progress_monitor
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wb_transaction_progress_monitor
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(
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(
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Target_Base_Addr_R[1] + 64, // expected address
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Target_Base_Addr_R[1] + 64, // expected address
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1'b0, // expected operation R/W
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1'b0, // expected operation R/W
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1, // expected number transfers
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1, // expected number transfers
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| Line 19505... |
Line 19510... |
1, // number of transfers
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1, // number of transfers
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`Test_Target_Normal_Completion // expected target termination
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`Test_Target_Normal_Completion // expected target termination
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) ;
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) ;
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end
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end
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@(posedge pci_clock) ;
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do_pause(1) ;
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while (FRAME !== 1'b1 || IRDY !== 1'b1)
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while (FRAME !== 1'b1 || IRDY !== 1'b1)
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@(posedge pci_clock) ;
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@(posedge pci_clock) ;
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|
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@(posedge pci_clock) ;
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@(posedge pci_clock) ;
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#1 ;
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#1 ;
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| Line 19564... |
Line 19569... |
1, // number of transfers
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1, // number of transfers
|
`Test_Target_Retry_On // expected target termination
|
`Test_Target_Retry_On // expected target termination
|
) ;
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) ;
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end
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end
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|
|
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do_pause(1) ;
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wb_transaction_progress_monitor
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wb_transaction_progress_monitor
|
(
|
(
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Target_Base_Addr_R[1] + 128, // expected address
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Target_Base_Addr_R[1] + 128, // expected address
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1'b0, // expected operation R/W
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1'b0, // expected operation R/W
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1, // expected number transfers
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1, // expected number transfers
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| Line 19608... |
Line 19614... |
1, // number of transfers
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1, // number of transfers
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`Test_Target_Normal_Completion // expected target termination
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`Test_Target_Normal_Completion // expected target termination
|
) ;
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) ;
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end
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end
|
|
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@(posedge pci_clock) ;
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do_pause(1) ;
|
while (FRAME !== 1'b1 || IRDY !== 1'b1)
|
while (FRAME !== 1'b1 || IRDY !== 1'b1)
|
@(posedge pci_clock) ;
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@(posedge pci_clock) ;
|
|
|
@(posedge pci_clock) ;
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@(posedge pci_clock) ;
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#1 ;
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#1 ;
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