| Line 37... |
Line 37... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.12 2002/10/21 13:04:30 mihad
|
|
// Changed BIST signal names etc..
|
|
//
|
// Revision 1.11 2002/10/11 12:03:12 mihad
|
// Revision 1.11 2002/10/11 12:03:12 mihad
|
// The testcase I just added in previous revision repaired
|
// The testcase I just added in previous revision repaired
|
//
|
//
|
// Revision 1.10 2002/10/11 10:08:57 mihad
|
// Revision 1.10 2002/10/11 10:08:57 mihad
|
// Added additional testcase and changed rst name in BIST to trst
|
// Added additional testcase and changed rst name in BIST to trst
|
| Line 845... |
Line 848... |
// first - reset logic
|
// first - reset logic
|
do_reset ;
|
do_reset ;
|
|
|
// if BIST is implemented, give it a go
|
// if BIST is implemented, give it a go
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
run_bist_test ;
|
// run_bist_test ;
|
|
scanb_rst <= #1 1'b1 ;
|
`endif
|
`endif
|
test_initial_conf_values ;
|
test_initial_conf_values ;
|
|
|
next_test_name[79:0] <= "Initing...";
|
next_test_name[79:0] <= "Initing...";
|
test_target_response[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1 ;
|
test_target_response[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1 ;
|
| Line 920... |
Line 924... |
|
|
`ifdef HOST
|
`ifdef HOST
|
iack_cycle ;
|
iack_cycle ;
|
`endif
|
`endif
|
|
|
|
test_master_overload ;
|
|
|
end
|
end
|
|
|
`ifdef DISABLE_COMPLETION_EXPIRED_TESTS
|
`ifdef DISABLE_COMPLETION_EXPIRED_TESTS
|
`else
|
`else
|
master_completion_expiration ;
|
master_completion_expiration ;
|
| Line 942... |
Line 948... |
$display("########################################################################") ;
|
$display("########################################################################") ;
|
$display("########################################################################") ;
|
$display("########################################################################") ;
|
|
|
$display("Testing PCI target images' features!") ;
|
$display("Testing PCI target images' features!") ;
|
configure_bridge_target_base_addresses ;
|
configure_bridge_target_base_addresses ;
|
|
|
`ifdef TEST_CONF_CYCLE_TYPE1_REFERENCE
|
`ifdef TEST_CONF_CYCLE_TYPE1_REFERENCE
|
test_conf_cycle_type1_reference ;
|
test_conf_cycle_type1_reference ;
|
`endif
|
`endif
|
|
|
`ifdef HOST
|
`ifdef HOST
|
| Line 996... |
Line 1001... |
test_wb_error_rd ;
|
test_wb_error_rd ;
|
|
|
target_fast_back_to_back ;
|
target_fast_back_to_back ;
|
target_disconnects ;
|
target_disconnects ;
|
|
|
|
test_target_overload ;
|
|
|
if ( target_io_image !== -1 )
|
if ( target_io_image !== -1 )
|
test_target_abort( target_io_image ) ;
|
test_target_abort( target_io_image ) ;
|
$display(" ") ;
|
$display(" ") ;
|
$display("PCI target images' tests finished!") ;
|
$display("PCI target images' tests finished!") ;
|
|
|
| Line 1013... |
Line 1020... |
$display(" ") ;
|
$display(" ") ;
|
$display("PCI transaction ordering tests finished!") ;
|
$display("PCI transaction ordering tests finished!") ;
|
end
|
end
|
end
|
end
|
|
|
|
tb_init_waits = 0 ;
|
|
tb_subseq_waits = 0 ;
|
|
|
`ifdef WB_CLOCK_FOLLOWS_PCI_CLOCK
|
`ifdef WB_CLOCK_FOLLOWS_PCI_CLOCK
|
test_target_response[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1 ;
|
test_target_response[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1 ;
|
test_target_response[`TARGET_ENCODED_INIT_WAITSTATES] = 0 ;
|
test_target_response[`TARGET_ENCODED_INIT_WAITSTATES] = 0 ;
|
test_target_response[`TARGET_ENCODED_SUBS_WAITSTATES] = 0 ;
|
test_target_response[`TARGET_ENCODED_SUBS_WAITSTATES] = 0 ;
|
test_target_response[`TARGET_ENCODED_DEVSEL_SPEED] = 0 ;
|
test_target_response[`TARGET_ENCODED_DEVSEL_SPEED] = 0 ;
|
| Line 1035... |
Line 1045... |
`endif
|
`endif
|
|
|
target_special_corner_case_test ;
|
target_special_corner_case_test ;
|
`endif
|
`endif
|
|
|
|
tb_init_waits = 0 ;
|
|
tb_subseq_waits = 0 ;
|
|
|
test_summary ;
|
test_summary ;
|
|
|
$fclose(wbu_mon_log_file_desc | pciu_mon_log_file_desc | pci_mon_log_file_desc) ;
|
$fclose(wbu_mon_log_file_desc | pciu_mon_log_file_desc | pci_mon_log_file_desc) ;
|
$stop ;
|
$stop ;
|
end
|
end
|
| Line 4963... |
Line 4976... |
// clear statuses
|
// clear statuses
|
config_write( pci_ctrl_offset, temp_val1, 4'b1111, ok ) ;
|
config_write( pci_ctrl_offset, temp_val1, 4'b1111, ok ) ;
|
test_name = "ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED" ;
|
test_name = "ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED" ;
|
fork
|
fork
|
begin
|
begin
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_MEM_WRITE, // normal command
|
`BC_MEM_WRITE, // normal command
|
| Line 4997... |
Line 5010... |
test_ok ;
|
test_ok ;
|
|
|
test_name = "ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED" ;
|
test_name = "ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED" ;
|
fork
|
fork
|
begin
|
begin
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_MEM_WRITE, // normal command
|
`BC_MEM_WRITE, // normal command
|
| Line 5065... |
Line 5078... |
config_write( pci_ctrl_offset, temp_val1, 4'b1111, ok ) ;
|
config_write( pci_ctrl_offset, temp_val1, 4'b1111, ok ) ;
|
|
|
test_name = "ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED" ;
|
test_name = "ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED" ;
|
fork
|
fork
|
begin
|
begin
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_MEM_WRITE, // normal command
|
`BC_MEM_WRITE, // normal command
|
| Line 5331... |
Line 5344... |
config_write( isr_offset, temp_val1, 4'b1111, ok ) ;
|
config_write( isr_offset, temp_val1, 4'b1111, ok ) ;
|
|
|
test_name = "ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED" ;
|
test_name = "ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED" ;
|
fork
|
fork
|
begin
|
begin
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_MEM_WRITE, // normal command
|
`BC_MEM_WRITE, // normal command
|
| Line 5469... |
Line 5482... |
config_write( isr_offset, temp_val1, 4'b1111, ok ) ;
|
config_write( isr_offset, temp_val1, 4'b1111, ok ) ;
|
|
|
test_name = "ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED" ;
|
test_name = "ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED" ;
|
fork
|
fork
|
begin
|
begin
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_MEM_WRITE, // normal command
|
`BC_MEM_WRITE, // normal command
|
| Line 5607... |
Line 5620... |
config_write( pci_ctrl_offset, (32'h0000_0147 | temp_val1), 4'b1111, ok ) ;
|
config_write( pci_ctrl_offset, (32'h0000_0147 | temp_val1), 4'b1111, ok ) ;
|
|
|
test_name = "ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED" ;
|
test_name = "ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED" ;
|
fork
|
fork
|
begin
|
begin
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_MEM_WRITE, // normal command
|
`BC_MEM_WRITE, // normal command
|
| Line 5874... |
Line 5887... |
config_write( isr_offset, temp_val1, 4'b1111, ok ) ;
|
config_write( isr_offset, temp_val1, 4'b1111, ok ) ;
|
|
|
test_name = "ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED" ;
|
test_name = "ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED" ;
|
fork
|
fork
|
begin
|
begin
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_MEM_WRITE, // normal command
|
`BC_MEM_WRITE, // normal command
|
| Line 5908... |
Line 5921... |
test_ok ;
|
test_ok ;
|
|
|
test_name = "ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED" ;
|
test_name = "ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED" ;
|
fork
|
fork
|
begin
|
begin
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_MEM_WRITE, // normal command
|
`BC_MEM_WRITE, // normal command
|
| Line 5976... |
Line 5989... |
config_write( pci_ctrl_offset, temp_val1, 4'b1111, ok ) ;
|
config_write( pci_ctrl_offset, temp_val1, 4'b1111, ok ) ;
|
|
|
test_name = "ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED" ;
|
test_name = "ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED" ;
|
fork
|
fork
|
begin
|
begin
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'hAAAA_AAAA, // first part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
32'h5555_5555, // second part of address in dual address cycle
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_MEM_WRITE, // normal command
|
`BC_MEM_WRITE, // normal command
|
| Line 8647... |
Line 8660... |
PCIU_IO_WRITE( `Test_Master_1, pci_image_base, 32'h5555_5555, 4'h0, 1, `Test_Target_Retry_On) ;
|
PCIU_IO_WRITE( `Test_Master_1, pci_image_base, 32'h5555_5555, 4'h0, 1, `Test_Target_Retry_On) ;
|
|
|
do_pause( 1 ) ;
|
do_pause( 1 ) ;
|
end
|
end
|
begin
|
begin
|
pci_transaction_progress_monitor( pci_image_base, `BC_MEM_WRITE, 0, 0, 1'b1, 1'b0, 1'b0, ok ) ;
|
pci_transaction_progress_monitor( pci_image_base, ((target_mem_image == 1) ? `BC_MEM_WRITE : `BC_IO_WRITE), 0, 0, 1'b1, 1'b0, 1'b0, ok ) ;
|
end
|
end
|
join
|
join
|
|
|
// try posting a write through wb_slave - it musn't go through since delayed read completion is present in PCI target unit
|
// try posting a write through wb_slave - it musn't go through since delayed read completion is present in PCI target unit
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
|
| Line 9195... |
Line 9208... |
output ok ;
|
output ok ;
|
reg in_use ;
|
reg in_use ;
|
integer deadlock_counter ;
|
integer deadlock_counter ;
|
integer transfer_counter ;
|
integer transfer_counter ;
|
integer deadlock_max_val ;
|
integer deadlock_max_val ;
|
|
reg [2:0] slave_termination ;
|
|
reg cab_asserted ;
|
begin:main
|
begin:main
|
if ( in_use === 1 )
|
if ( in_use === 1 )
|
begin
|
begin
|
$display("wb_transaction_progress_monitor task re-entered! Time %t ", $time) ;
|
$display("wb_transaction_progress_monitor task re-entered! Time %t ", $time) ;
|
ok = 0 ;
|
ok = 0 ;
|
| Line 9220... |
Line 9235... |
// maximum wb clock cycles
|
// maximum wb clock cycles
|
deadlock_max_val = deadlock_max_val / (1/`WB_FREQ) ;
|
deadlock_max_val = deadlock_max_val / (1/`WB_FREQ) ;
|
|
|
in_use = 1 ;
|
in_use = 1 ;
|
ok = 1 ;
|
ok = 1 ;
|
|
cab_asserted = 0 ;
|
|
|
fork
|
fork
|
begin:wait_start
|
begin:wait_start
|
deadlock_counter = 0 ;
|
deadlock_counter = 0 ;
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
| Line 9294... |
Line 9310... |
while( CYC_O !== 1 )
|
while( CYC_O !== 1 )
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
|
|
while( (CYC_O === 1) && ((transfer_counter <= `PCIW_DEPTH) || (transfer_counter <= `PCIR_DEPTH)) )
|
while( (CYC_O === 1) && ((transfer_counter <= `PCIW_DEPTH) || (transfer_counter <= `PCIR_DEPTH)) )
|
begin
|
begin
|
if ( (STB_O === 1) && (ACK_I === 1) )
|
|
|
if (!cab_asserted)
|
|
cab_asserted = (CAB_O !== 1'b0) ;
|
|
|
|
if (STB_O === 1)
|
|
begin
|
|
slave_termination = {ACK_I, ERR_I, RTY_I} ;
|
|
if (ACK_I)
|
transfer_counter = transfer_counter + 1 ;
|
transfer_counter = transfer_counter + 1 ;
|
|
end
|
@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
|
end
|
end
|
|
|
|
if (cab_asserted)
|
|
begin
|
|
// cab was sampled asserted
|
|
// if number of transfers was less than 2 - check for extraordinary terminations
|
|
if (transfer_counter < 2)
|
|
begin
|
|
// if cycle was terminated because of no response, error or retry, than it is OK to have CAB_O asserted while transfering 0 or 1 data.
|
|
// any other cases are wrong
|
|
case (slave_termination)
|
|
3'b000:begin end
|
|
3'b001:begin end
|
|
3'b010:begin end
|
|
default:begin
|
|
ok = 0 ;
|
|
$display("Time %t", $time) ;
|
|
$display("WB_MASTER asserted CAB_O for single transfer") ;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
// if cab is not asserted, then WB_MASTER should not read more than one data.
|
|
if (transfer_counter > 1)
|
|
begin
|
|
ok = 0 ;
|
|
$display("Time %t", $time) ;
|
|
$display("WB_MASTER didn't assert CAB_O for consecutive block transfer") ;
|
|
end
|
|
end
|
|
|
if ( check_transfers === 1 )
|
if ( check_transfers === 1 )
|
begin
|
begin
|
if ( transfer_counter !== num_of_transfers )
|
if ( transfer_counter !== num_of_transfers )
|
begin
|
begin
|
$display("wb_transaction_progress_monitor detected unexpected transaction! Time %t ", $time) ;
|
$display("wb_transaction_progress_monitor detected unexpected transaction! Time %t ", $time) ;
|
| Line 17060... |
Line 17115... |
fork
|
fork
|
begin
|
begin
|
DO_REF ("MEM_WRITE ", `Test_Master_1, pci_address[PCI_BUS_DATA_RANGE:0],
|
DO_REF ("MEM_WRITE ", `Test_Master_1, pci_address[PCI_BUS_DATA_RANGE:0],
|
PCI_COMMAND_MEMORY_WRITE, data[PCI_BUS_DATA_RANGE:0],
|
PCI_COMMAND_MEMORY_WRITE, data[PCI_BUS_DATA_RANGE:0],
|
byte_enables,
|
byte_enables,
|
(tb_subseq_waits != 4) ? expect_length : (expect_length + 1), `Test_No_Addr_Perr, `Test_No_Data_Perr,
|
expect_length + 1, `Test_No_Addr_Perr, `Test_No_Data_Perr,
|
8'h0_0, `Test_One_Zero_Target_WS,
|
8'h0_0, `Test_One_Zero_Target_WS,
|
`Test_Devsel_Medium, `Test_No_Fast_B2B,
|
`Test_Devsel_Medium, `Test_No_Fast_B2B,
|
(tb_subseq_waits != 4) ? `Test_Target_Disc_On : `Test_Target_Retry_On, `Test_Expect_No_Master_Abort);
|
`Test_Target_Retry_On, `Test_Expect_No_Master_Abort);
|
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
| Line 17103... |
Line 17158... |
fork
|
fork
|
begin
|
begin
|
DO_REF ("MEM_WRITE ", `Test_Master_1, pci_address[PCI_BUS_DATA_RANGE:0],
|
DO_REF ("MEM_WRITE ", `Test_Master_1, pci_address[PCI_BUS_DATA_RANGE:0],
|
PCI_COMMAND_MEMORY_WRITE, data[PCI_BUS_DATA_RANGE:0],
|
PCI_COMMAND_MEMORY_WRITE, data[PCI_BUS_DATA_RANGE:0],
|
byte_enables,
|
byte_enables,
|
(tb_subseq_waits != 4) ? (expect_length + 1) : (expect_length + 2) , `Test_No_Addr_Perr, `Test_No_Data_Perr,
|
expect_length + 2, `Test_No_Addr_Perr, `Test_No_Data_Perr,
|
8'h0_0, `Test_One_Zero_Target_WS,
|
8'h0_0, `Test_One_Zero_Target_WS,
|
`Test_Devsel_Medium, `Test_No_Fast_B2B,
|
`Test_Devsel_Medium, `Test_No_Fast_B2B,
|
(tb_subseq_waits != 4) ? `Test_Target_Disc_Before : `Test_Target_Retry_Before, `Test_Expect_No_Master_Abort);
|
`Test_Target_Retry_Before, `Test_Expect_No_Master_Abort);
|
do_pause( 3 ) ;
|
do_pause( 3 ) ;
|
|
|
while ( FRAME !== 1 || IRDY !== 1 )
|
while ( FRAME !== 1 || IRDY !== 1 )
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
|
|
| Line 17863... |
Line 17918... |
0, // type of configuration cycle
|
0, // type of configuration cycle
|
4'b0001, // byte enables
|
4'b0001, // byte enables
|
32'h0000_0044 // data
|
32'h0000_0044 // data
|
) ;
|
) ;
|
|
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
Address, // first part of address in dual address cycle
|
Address, // first part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
`BC_IACK, // dual address cycle command
|
`BC_IACK, // dual address cycle command
|
`BC_IACK, // normal command
|
`BC_IACK, // normal command
|
| Line 17885... |
Line 17940... |
test_fail("PCI Target shouldn't responded on unsuported bus command IACK") ;
|
test_fail("PCI Target shouldn't responded on unsuported bus command IACK") ;
|
end
|
end
|
|
|
$display(" Master abort testing with unsuported bus command to image %d (BC is SPECIAL)!", image_num) ;
|
$display(" Master abort testing with unsuported bus command to image %d (BC is SPECIAL)!", image_num) ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIAL" ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIAL" ;
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
Address, // first part of address in dual address cycle
|
Address, // first part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
`BC_SPECIAL, // dual address cycle command
|
`BC_SPECIAL, // dual address cycle command
|
`BC_SPECIAL, // normal command
|
`BC_SPECIAL, // normal command
|
| Line 17907... |
Line 17962... |
test_fail("PCI Target shouldn't responded on unsuported bus command SPECIAL") ;
|
test_fail("PCI Target shouldn't responded on unsuported bus command SPECIAL") ;
|
end
|
end
|
|
|
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED0)!", image_num) ;
|
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED0)!", image_num) ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0" ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0" ;
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
Address, // first part of address in dual address cycle
|
Address, // first part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
`BC_RESERVED0, // dual address cycle command
|
`BC_RESERVED0, // dual address cycle command
|
`BC_RESERVED0, // normal command
|
`BC_RESERVED0, // normal command
|
| Line 17929... |
Line 17984... |
test_fail("PCI Target shouldn't responded on unsuported bus command RESERVED0") ;
|
test_fail("PCI Target shouldn't responded on unsuported bus command RESERVED0") ;
|
end
|
end
|
|
|
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED1)", image_num) ;
|
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED1)", image_num) ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1" ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1" ;
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
Address, // first part of address in dual address cycle
|
Address, // first part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
`BC_RESERVED1, // dual address cycle command
|
`BC_RESERVED1, // dual address cycle command
|
`BC_RESERVED1, // normal command
|
`BC_RESERVED1, // normal command
|
| Line 17951... |
Line 18006... |
test_fail("PCI Target shouldn't responded on unsuported bus command RESERVED1") ;
|
test_fail("PCI Target shouldn't responded on unsuported bus command RESERVED1") ;
|
end
|
end
|
|
|
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED2)!", image_num) ;
|
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED2)!", image_num) ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2" ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2" ;
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
Address, // first part of address in dual address cycle
|
Address, // first part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
`BC_RESERVED2, // dual address cycle command
|
`BC_RESERVED2, // dual address cycle command
|
`BC_RESERVED2, // normal command
|
`BC_RESERVED2, // normal command
|
| Line 17973... |
Line 18028... |
test_fail("PCI Target shouldn't responded on unsuported bus command RESERVED2") ;
|
test_fail("PCI Target shouldn't responded on unsuported bus command RESERVED2") ;
|
end
|
end
|
|
|
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED3)!", image_num) ;
|
$display(" Master abort testing with unsuported bus command to image %d (BC is RESERVED3)!", image_num) ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3" ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3" ;
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
Address, // first part of address in dual address cycle
|
Address, // first part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
`BC_RESERVED3, // dual address cycle command
|
`BC_RESERVED3, // dual address cycle command
|
`BC_RESERVED3, // normal command
|
`BC_RESERVED3, // normal command
|
| Line 17997... |
Line 18052... |
|
|
$display("PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and ") ;
|
$display("PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and ") ;
|
$display(" byte enables are different than first bus command (DUAL_ADDR_CYC)!") ;
|
$display(" byte enables are different than first bus command (DUAL_ADDR_CYC)!") ;
|
$display(" Master abort testing with unsuported bus command to image %d (BC is DUAL_ADDR_CYC)!", image_num) ;
|
$display(" Master abort testing with unsuported bus command to image %d (BC is DUAL_ADDR_CYC)!", image_num) ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYC" ;
|
test_name = "MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYC" ;
|
ipci_unsupported_commands_master.master_reference
|
ipci_unsupported_commands_master.unsupported_reference
|
(
|
(
|
Address, // first part of address in dual address cycle
|
Address, // first part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
Address, // second part of address in dual address cycle
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_DUAL_ADDR_CYC, // dual address cycle command
|
`BC_MEM_WRITE, // normal command
|
`BC_MEM_WRITE, // normal command
|
| Line 19891... |
Line 19946... |
end
|
end
|
end
|
end
|
endtask // master_special_corner_case_test
|
endtask // master_special_corner_case_test
|
`endif
|
`endif
|
|
|
|
task test_target_overload ;
|
|
reg ok_pci ;
|
|
reg ok_wb ;
|
|
reg ok ;
|
|
reg [2:0] test_image_num ;
|
|
reg addr_translated ;
|
|
integer transfered ;
|
|
reg [2:0] received_termination ;
|
|
integer total_transfers ;
|
|
reg [31:0] transaction_sizes [0:1024] ;
|
|
integer pci_transaction_num ;
|
|
integer wb_transaction_num ;
|
|
reg [31:0] current_wb_address ;
|
|
reg io_mapped ;
|
|
integer init_waits_backup ;
|
|
integer current_size ;
|
|
begin:main
|
|
init_waits_backup = tb_init_waits ;
|
|
tb_init_waits = 0 ;
|
|
|
|
`ifdef HOST
|
|
io_mapped = 1'b0 ;
|
|
`endif
|
|
|
|
test_image_num = 'd1 ;
|
|
`ifdef GUEST
|
|
io_mapped = `PCI_BA1_MEM_IO ;
|
|
`endif
|
|
|
|
`ifdef PCI_IMAGE2
|
|
test_image_num = 'd2 ;
|
|
`ifdef GUEST
|
|
io_mapped = `PCI_BA2_MEM_IO ;
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef PCI_IMAGE3
|
|
test_image_num = 'd3 ;
|
|
`ifdef GUEST
|
|
io_mapped = `PCI_BA3_MEM_IO ;
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef PCI_IMAGE4
|
|
test_image_num = 'd4 ;
|
|
`ifdef GUEST
|
|
io_mapped = `PCI_BA4_MEM_IO ;
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef PCI_IMAGE5
|
|
test_image_num = 'd5 ;
|
|
`ifdef GUEST
|
|
io_mapped = `PCI_BA5_MEM_IO ;
|
|
`endif
|
|
`endif
|
|
|
|
test_name = "PCI TARGET OVERLOAD" ;
|
|
// configure target image 1 via bus accesses
|
|
pci_configure_pci_target_image
|
|
(
|
|
1'b1, // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
|
|
test_image_num, // image number
|
|
Target_Base_Addr_R[test_image_num], // base address
|
|
Target_Addr_Mask_R[test_image_num], // address mask
|
|
Target_Tran_Addr_R[test_image_num], // translation address
|
|
1'b0, // io/mem mapping select
|
|
1'b0, // prefetch enable
|
|
1'b1, // address translation enable
|
|
ok // finished succesfully
|
|
);
|
|
if (ok !== 1'b1)
|
|
begin
|
|
test_fail("configuration of PCI Target Image didn't succeede") ;
|
|
tb_init_waits = init_waits_backup ;
|
|
#1 disable main ;
|
|
end
|
|
|
|
`ifdef ADDR_TRAN_IMPL
|
|
addr_translated = 1'b1 ;
|
|
`else
|
|
addr_translated = 1'b0 ;
|
|
`endif
|
|
|
|
// set wb slave's response to max wait cycles
|
|
wishbone_slave.cycle_response
|
|
(
|
|
3'b100, // ACK, ERR, RTY termination
|
|
tb_subseq_waits, // wait cycles before response
|
|
0 // number of retries before acknowledge
|
|
) ;
|
|
|
|
ok_pci = 1 ;
|
|
ok_wb = 1 ;
|
|
current_wb_address = pci_to_wb_addr_convert
|
|
(
|
|
Target_Base_Addr_R[test_image_num], // pci address
|
|
Target_Tran_Addr_R[test_image_num], // translation address
|
|
addr_translated
|
|
);
|
|
current_wb_address = current_wb_address & Target_Addr_Mask_R[test_image_num] ;
|
|
|
|
for (current_size = 2 ; (current_size <= 1024) && ok_pci && ok_wb && ok ; current_size = current_size * 2)
|
|
begin
|
|
|
|
total_transfers = 0 ;
|
|
pci_transaction_num = 0 ;
|
|
wb_transaction_num = 0 ;
|
|
|
|
current_wb_address = current_wb_address & Target_Addr_Mask_R[test_image_num] ;
|
|
current_wb_address = current_wb_address + (('d1024 - current_size) * 4) ;
|
|
fork
|
|
begin
|
|
while ((total_transfers < current_size) && ok_pci && ok_wb && ok)
|
|
begin
|
|
// try transfering 4kB with no wait cycles through the target
|
|
ipci_unsupported_commands_master.normal_write_transfer
|
|
(
|
|
// always write to the end of the 4kB window
|
|
(('d1024 - current_size) * 4) + Target_Base_Addr_R[test_image_num] + (4 * total_transfers), // start_address
|
|
io_mapped ? `BC_IO_WRITE : `BC_MEM_WRITE, // bus_command
|
|
(current_size - total_transfers), // size
|
|
4 - tb_subseq_waits[2:0], // subsequent wait cycles
|
|
transfered, // actual_transfer
|
|
received_termination // received_termination
|
|
);
|
|
if (transfered > 0)
|
|
begin
|
|
transaction_sizes[pci_transaction_num] = transfered ;
|
|
pci_transaction_num = pci_transaction_num + 1'b1 ;
|
|
end
|
|
total_transfers = total_transfers + transfered ;
|
|
if (received_termination > 2) // terminations with numbers 3(Target Abort), 4(Master Abort) and 5(Error) are not allowed
|
|
begin
|
|
ok_pci = 0 ;
|
|
if (received_termination == 3)
|
|
test_fail("PCI Target signalled Target Abort") ;
|
|
|
|
if (received_termination == 4)
|
|
test_fail("PCI Master generated Master Abort") ;
|
|
|
|
if (received_termination == 5)
|
|
test_fail("PCI behavioral master signaled severe error") ;
|
|
end
|
|
end
|
|
end
|
|
begin:wb_monitoring
|
|
while (((total_transfers < current_size) || (pci_transaction_num > wb_transaction_num)) && ok_pci && ok_wb && ok)
|
|
begin
|
|
wait(pci_transaction_num > wb_transaction_num) ;
|
|
wb_transaction_progress_monitor
|
|
(
|
|
current_wb_address, //address
|
|
1'b1, //write/read
|
|
transaction_sizes[wb_transaction_num], //num_of_transfers
|
|
1'b1, //check_transfers
|
|
ok_wb // success/fail
|
|
);
|
|
current_wb_address = current_wb_address + (transaction_sizes[wb_transaction_num] * 4) ;
|
|
wb_transaction_num = wb_transaction_num + 1'b1 ;
|
|
if (ok_wb !== 1'b1)
|
|
begin
|
|
test_fail("WB Transaction progress monitor detected invalid transaction or none at all on WB bus");
|
|
end
|
|
end
|
|
|
|
wb_transaction_num = wb_transaction_num - 1'b1 ;
|
|
current_wb_address = current_wb_address - (transaction_sizes[wb_transaction_num] * 4) ;
|
|
|
|
if (ok)
|
|
#1 disable pci_monitoring ;
|
|
end
|
|
begin:pci_monitoring
|
|
@(error_event_int) ;
|
|
test_fail("PCI Bus monitor detected invalid operation on PCI bus") ;
|
|
ok = 0 ;
|
|
ok_pci = 0 ;
|
|
ok_wb = 0 ;
|
|
end
|
|
join
|
|
end
|
|
|
|
if ((ok && ok_wb && ok_pci) === 1'b1)
|
|
test_ok ;
|
|
|
|
tb_init_waits = init_waits_backup ;
|
|
end
|
|
endtask // test_target_overload
|
|
|
|
task test_master_overload ;
|
|
reg ok_pci ;
|
|
reg ok_wb ;
|
|
reg ok ;
|
|
reg [2:0] test_image_num ;
|
|
integer transfered ;
|
|
reg [2:0] received_termination ;
|
|
integer total_transfers ;
|
|
reg [31:0] transaction_sizes [0:1024] ;
|
|
integer pci_transaction_num ;
|
|
integer wb_transaction_num ;
|
|
reg [31:0] current_pci_address ;
|
|
integer init_waits_backup ;
|
|
integer current_size ;
|
|
|
|
reg `WRITE_STIM_TYPE write_data ;
|
|
|
|
reg `WRITE_RETURN_TYPE write_status ;
|
|
reg `WB_TRANSFER_FLAGS write_flags ;
|
|
|
|
reg [31:0] image_base ;
|
|
reg [31:0] target_address ;
|
|
|
|
integer i ;
|
|
begin:main
|
|
|
|
// set behavioral target to respond normally
|
|
test_target_response[`TARGET_ENCODED_TERMINATION] = `Test_Target_Normal_Completion ;
|
|
test_target_response[`TARGET_ENCODED_TERMINATE_ON] = 0 ;
|
|
|
|
test_image_num = 'd1 ;
|
|
|
|
`ifdef WB_IMAGE2
|
|
test_image_num = 'd2 ;
|
|
`endif
|
|
|
|
`ifdef WB_IMAGE3
|
|
test_image_num = 'd3 ;
|
|
`endif
|
|
|
|
`ifdef WB_IMAGE4
|
|
test_image_num = 'd4 ;
|
|
`endif
|
|
|
|
`ifdef WB_IMAGE5
|
|
test_image_num = 'd5 ;
|
|
`endif
|
|
|
|
test_name = "MASTER OVERLOAD" ;
|
|
|
|
target_address = `BEH_TAR1_MEM_START ;
|
|
image_base = 0 ;
|
|
image_base[`PCI_BASE_ADDR0_MATCH_RANGE] = target_address[`PCI_BASE_ADDR0_MATCH_RANGE] ;
|
|
|
|
target_address[31:(32 - `WB_NUM_OF_DEC_ADDR_LINES)] = image_base[31:(32 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
|
target_address[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = image_base[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] ;
|
|
|
|
write_flags = 0 ;
|
|
write_flags`INIT_WAITS = tb_init_waits ;
|
|
write_flags`SUBSEQ_WAITS = tb_subseq_waits ;
|
|
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
|
write_flags`WB_TRANSFER_CAB = 1'b1 ;
|
|
|
|
pci_configure_wb_slave_image
|
|
(
|
|
1'b1, // use_bus
|
|
test_image_num, // image_num
|
|
image_base, // base address
|
|
32'hFFFF_FFFF, // address mask
|
|
32'h0000_0000, // translation address
|
|
1'b0, // io/mem mapping select
|
|
1'b1, // prefetch enable
|
|
1'b0, // address translation enable
|
|
1'b1, // memory read line enable
|
|
ok // finished succesfully
|
|
) ;
|
|
|
|
if (ok !== 1'b1)
|
|
begin
|
|
test_fail("WB image configuration failed") ;
|
|
disable main ;
|
|
end
|
|
|
|
// fill wishbone master's memory with data - inverted addresses
|
|
write_data = 0 ;
|
|
for (i = 0 ; i < 1024 ; i = i + 1)
|
|
begin
|
|
write_data`WRITE_ADDRESS = image_base + (4 * i) ;
|
|
write_data`WRITE_DATA = ~(write_data`WRITE_ADDRESS);
|
|
wishbone_master.blk_write_data[i] = write_data ;
|
|
end
|
|
|
|
ok_wb = 1 ;
|
|
ok_pci = 1 ;
|
|
|
|
total_transfers = 0 ;
|
|
|
|
for (current_size = 2 ; (current_size <= 1024) && ok_pci && ok_wb && ok ; current_size = current_size * 2)
|
|
begin
|
|
|
|
total_transfers = 0 ;
|
|
pci_transaction_num = 0 ;
|
|
wb_transaction_num = 0 ;
|
|
|
|
current_pci_address = image_base ;
|
|
fork
|
|
begin
|
|
while ((total_transfers < current_size) && ok_pci && ok_wb && ok)
|
|
begin
|
|
// try transfering 4kB with no wait cycles through the wb slave unit
|
|
write_flags`WB_TRANSFER_SIZE = current_size - total_transfers ;
|
|
wishbone_master.wb_block_write(write_flags, write_status) ;
|
|
if (write_status`CYC_ERR || ((write_status`CYC_ERR !== 1'b1) && (write_status`CYC_RTY !== 1'b1) && (write_status`CYC_ACK !== 1'b1)))
|
|
begin
|
|
test_fail("Wishbone slave signaled an error or did not respond to normal write access") ;
|
|
ok_wb = 0 ;
|
|
end
|
|
|
|
transfered = write_status`CYC_ACTUAL_TRANSFER ;
|
|
if (transfered > 0)
|
|
begin
|
|
transaction_sizes[wb_transaction_num] = transfered ;
|
|
wb_transaction_num = wb_transaction_num + 1'b1 ;
|
|
end
|
|
total_transfers = total_transfers + transfered ;
|
|
end
|
|
end
|
|
begin:pci_models_monitoring
|
|
while (((total_transfers < current_size) || (wb_transaction_num > pci_transaction_num)) && ok_pci && ok_wb && ok)
|
|
begin
|
|
wait(wb_transaction_num > pci_transaction_num) ;
|
|
pci_transaction_progress_monitor
|
|
(
|
|
current_pci_address, // address
|
|
`BC_MEM_WRITE, // bus_command
|
|
transaction_sizes[pci_transaction_num], // num_of_transfers
|
|
0, // num_of_cycles
|
|
1'b1, // check_transfers
|
|
1'b0, // check_cycles
|
|
1'b0, // doing_fast_back_to_back
|
|
ok_pci // ok
|
|
) ;
|
|
|
|
pci_transaction_num = pci_transaction_num + 1'b1 ;
|
|
if (ok_pci !== 1'b1)
|
|
begin
|
|
test_fail("PCI Transaction progress monitor detected invalid transaction or none at all on PCI bus");
|
|
end
|
|
end
|
|
|
|
if (ok)
|
|
#1 disable pci_monitoring ;
|
|
end
|
|
begin:pci_monitoring
|
|
@(error_event_int) ;
|
|
test_fail("PCI Bus monitor detected invalid operation on PCI bus") ;
|
|
ok = 0 ;
|
|
ok_pci = 0 ;
|
|
ok_wb = 0 ;
|
|
end
|
|
join
|
|
end
|
|
|
|
// disable the image
|
|
pci_configure_wb_slave_image
|
|
(
|
|
1'b1, // use_bus
|
|
test_image_num, // image_num
|
|
image_base, // base address
|
|
32'h0000_0000, // address mask
|
|
32'h0000_0000, // translation address
|
|
1'b0, // io/mem mapping select
|
|
1'b1, // prefetch enable
|
|
1'b0, // address translation enable
|
|
1'b1, // memory read line enable
|
|
ok // finished succesfully
|
|
) ;
|
|
|
|
if (ok !== 1'b1)
|
|
begin
|
|
test_fail("WB image configuration failed") ;
|
|
disable main ;
|
|
end
|
|
|
|
if ((ok && ok_wb && ok_pci) === 1'b1)
|
|
test_ok ;
|
|
end
|
|
endtask // test_master_overload
|
|
|
task test_fail ;
|
task test_fail ;
|
input [7999:0] failure_reason ;
|
input [7999:0] failure_reason ;
|
reg [8007:0] display_failure ;
|
reg [8007:0] display_failure ;
|
reg [799:0] display_test ;
|
reg [799:0] display_test ;
|
begin
|
begin
|
| Line 19972... |
Line 20405... |
$fdisplay( tb_log_file, " - WISHBONE Behavioral Devices' Initial Wait States = %d", tb_init_waits) ;
|
$fdisplay( tb_log_file, " - WISHBONE Behavioral Devices' Initial Wait States = %d", tb_init_waits) ;
|
$fdisplay( tb_log_file, " - WISHBONE Behavioral Devices' Subsequent Wait States = %d", tb_subseq_waits) ;
|
$fdisplay( tb_log_file, " - WISHBONE Behavioral Devices' Subsequent Wait States = %d", tb_subseq_waits) ;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
`include "pci_bench_common_tasks.v"
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
