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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [system.v] - Diff between revs 73 and 81

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Rev 73 Rev 81
Line 37... Line 37...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.13  2003/01/21 16:06:50  mihad
 
// Bug fixes, testcases added.
 
//
// Revision 1.12  2002/10/21 13:04:30  mihad
// Revision 1.12  2002/10/21 13:04:30  mihad
// Changed BIST signal names etc..
// Changed BIST signal names etc..
//
//
// Revision 1.11  2002/10/11 12:03:12  mihad
// Revision 1.11  2002/10/11 12:03:12  mihad
// The testcase I just added in previous revision repaired
// The testcase I just added in previous revision repaired
Line 18923... Line 18926...
            $display("Completion expiration testing failed! Bridge failed to process single memory write! Time %t ", $time) ;
            $display("Completion expiration testing failed! Bridge failed to process single memory write! Time %t ", $time) ;
            test_fail("WB Slave state machine failed to post single memory write");
            test_fail("WB Slave state machine failed to post single memory write");
            disable main ;
            disable main ;
        end
        end
 
 
        // completion is present if wbr fifo for sure, since write proceeded ok, wait for completion to almost expire - 2^^16 cycles - 100
        // completion is present if wbr fifo for sure, since write proceeded ok, wait for completion to almost expire - 2^^16 cycles - 110
        repeat('h1_0000 - 100)
        repeat('h1_0000 - 110)
            @(posedge wb_clock) ;
            @(posedge wb_clock) ;
 
 
        // now perform a read
        // now perform a read
        read_data`READ_ADDRESS  = target_address + 4 ;
        read_data`READ_ADDRESS  = target_address + 4 ;
        read_data`READ_SEL      = 4'hF ;
        read_data`READ_SEL      = 4'hF ;
Line 18976... Line 18979...
            test_fail("because single memory write from WB to PCI didn't engage expected transaction on PCI bus") ;
            test_fail("because single memory write from WB to PCI didn't engage expected transaction on PCI bus") ;
            #1 disable monitors ;
            #1 disable monitors ;
        end
        end
 
 
        // wait for 2^^16 cycles, so monitor won't complain about waiting too long
        // wait for 2^^16 cycles, so monitor won't complain about waiting too long
        repeat('h1_0000 - 50)
        repeat('h1_0000 - 100)
            @(posedge wb_clock) ;
            @(posedge wb_clock) ;
 
 
        // monitor normal single memory read
        // monitor normal single memory read
        pci_transaction_progress_monitor( target_address + 4, `BC_MEM_READ, 1, 0, 1, 0, 0, ok ) ;
        pci_transaction_progress_monitor( target_address + 4, `BC_MEM_READ, 1, 0, 1, 0, 0, ok ) ;
        if ( ok !== 1 )
        if ( ok !== 1 )

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