| Line 37... |
Line 37... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2003/01/21 16:06:50 mihad
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// Bug fixes, testcases added.
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//
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// Revision 1.12 2002/10/21 13:04:30 mihad
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// Revision 1.12 2002/10/21 13:04:30 mihad
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// Changed BIST signal names etc..
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// Changed BIST signal names etc..
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//
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//
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// Revision 1.11 2002/10/11 12:03:12 mihad
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// Revision 1.11 2002/10/11 12:03:12 mihad
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// The testcase I just added in previous revision repaired
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// The testcase I just added in previous revision repaired
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| Line 18923... |
Line 18926... |
$display("Completion expiration testing failed! Bridge failed to process single memory write! Time %t ", $time) ;
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$display("Completion expiration testing failed! Bridge failed to process single memory write! Time %t ", $time) ;
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test_fail("WB Slave state machine failed to post single memory write");
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test_fail("WB Slave state machine failed to post single memory write");
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disable main ;
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disable main ;
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end
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end
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// completion is present if wbr fifo for sure, since write proceeded ok, wait for completion to almost expire - 2^^16 cycles - 100
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// completion is present if wbr fifo for sure, since write proceeded ok, wait for completion to almost expire - 2^^16 cycles - 110
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repeat('h1_0000 - 100)
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repeat('h1_0000 - 110)
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@(posedge wb_clock) ;
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@(posedge wb_clock) ;
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// now perform a read
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// now perform a read
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read_data`READ_ADDRESS = target_address + 4 ;
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read_data`READ_ADDRESS = target_address + 4 ;
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read_data`READ_SEL = 4'hF ;
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read_data`READ_SEL = 4'hF ;
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| Line 18976... |
Line 18979... |
test_fail("because single memory write from WB to PCI didn't engage expected transaction on PCI bus") ;
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test_fail("because single memory write from WB to PCI didn't engage expected transaction on PCI bus") ;
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#1 disable monitors ;
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#1 disable monitors ;
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end
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end
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// wait for 2^^16 cycles, so monitor won't complain about waiting too long
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// wait for 2^^16 cycles, so monitor won't complain about waiting too long
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repeat('h1_0000 - 50)
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repeat('h1_0000 - 100)
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@(posedge wb_clock) ;
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@(posedge wb_clock) ;
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// monitor normal single memory read
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// monitor normal single memory read
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pci_transaction_progress_monitor( target_address + 4, `BC_MEM_READ, 1, 0, 1, 0, 0, ok ) ;
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pci_transaction_progress_monitor( target_address + 4, `BC_MEM_READ, 1, 0, 1, 0, 0, ok ) ;
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if ( ok !== 1 )
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if ( ok !== 1 )
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