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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.10 2002/10/18 03:36:37 tadejm
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// Revision 1.10 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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// Changed wrong signal name scanb_sen into scanb_en.
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//
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//
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// Revision 1.9 2002/10/17 22:51:08 tadejm
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// Revision 1.9 2002/10/17 22:51:08 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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Line 562... |
else
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else
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if (in_count_en)
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if (in_count_en)
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
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end
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end
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wire [(PCIW_ADDR_LENGTH-2):0] wb_clk_sync_inGreyCount ;
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reg [(PCIW_ADDR_LENGTH-2):0] wb_clk_inGreyCount ;
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synchronizer_flop #((PCIW_ADDR_LENGTH - 1)) i_synchronizer_reg_inGreyCount
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(
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.data_in (inGreyCount),
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.clk_out (wb_clock_in),
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.sync_data_out (wb_clk_sync_inGreyCount),
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.async_reset (1'b0)
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) ;
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always@(posedge wb_clock_in or posedge pciw_clear)
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begin
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if (pciw_clear)
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wb_clk_inGreyCount <= #`FF_DELAY 1 ;
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else
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wb_clk_inGreyCount <= # `FF_DELAY wb_clk_sync_inGreyCount ;
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end
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always@(posedge wb_clock_in or posedge pciw_clear)
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always@(posedge wb_clock_in or posedge pciw_clear)
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begin
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begin
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if (pciw_clear)
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if (pciw_clear)
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begin
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begin
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outGreyCount[(PCIW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
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outGreyCount[(PCIW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
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Line 610... |
else
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else
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if (out_count_en)
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if (out_count_en)
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pciw_outTransactionCount <= #`FF_DELAY pciw_outTransactionCount + 1'b1 ;
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pciw_outTransactionCount <= #`FF_DELAY pciw_outTransactionCount + 1'b1 ;
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end
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end
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// transaction is ready when incoming transaction count is not equal to outgoing transaction count ( what comes in must come out )
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assign pciw_transaction_ready_out = wb_clk_inGreyCount != outGreyCount ;
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// anytime last entry of transaction is pulled out of fifo, transaction ready flag is cleared for at least one clock to prevent wrong operation
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// ( otherwise transaction ready would stay set for one additional clock even though next transaction was not ready )
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wire pciw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
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meta_flop #(0) i_meta_flop_transaction_ready
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(
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.rst_i (pciw_clear),
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.clk_i (wb_clock_in),
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.ld_i (out_count_en),
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.ld_val_i (1'b0),
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.en_i (1'b1),
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.d_i (pciw_transaction_ready_flop_i),
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.meta_q_o (pciw_transaction_ready_out)
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) ;
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assign pcir_transaction_ready_out = 1'b0 ;
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assign pcir_transaction_ready_out = 1'b0 ;
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endmodule
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endmodule
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