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[/] [pci/] [tags/] [rel_6/] [bench/] [verilog/] [pci_bus_monitor.v] - Diff between revs 15 and 35
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//===========================================================================
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//===========================================================================
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// $Id: pci_bus_monitor.v,v 1.1 2002-02-01 13:39:43 mihad Exp $
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// $Id: pci_bus_monitor.v,v 1.2 2002-03-21 07:35:50 mihad Exp $
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//
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//
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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//
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//
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// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.
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// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.
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// This module also has access to the individual PCI Bus OE
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// This module also has access to the individual PCI Bus OE
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//
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//
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//===========================================================================
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//===========================================================================
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// Note that master aborts are the norm on Special Cycles!
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// Note that master aborts are the norm on Special Cycles!
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`timescale 1ns/10ps
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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//`timescale 1ns/10ps
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module pci_bus_monitor (
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module pci_bus_monitor (
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pci_ext_ad, pci_ext_cbe_l, pci_ext_par,
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pci_ext_ad, pci_ext_cbe_l, pci_ext_par,
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pci_ext_frame_l, pci_ext_irdy_l,
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pci_ext_frame_l, pci_ext_irdy_l,
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pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,
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pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,
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