| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/10/11 10:09:01 mihad
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// Added additional testcase and changed rst name in BIST to trst
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//
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// Revision 1.4 2002/10/08 17:17:05 mihad
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// Revision 1.4 2002/10/08 17:17:05 mihad
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// Added BIST signals for RAMs.
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// Added BIST signals for RAMs.
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//
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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| Line 164... |
Line 167... |
PCI_SERRn_EN_OUT
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PCI_SERRn_EN_OUT
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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trst ,
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scanb_rst, // bist scan reset
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SO ,
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scanb_clk, // bist scan clock
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SI ,
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scanb_si, // bist scan serial in
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shift_DR ,
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scanb_so, // bist scan serial out
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capture_DR ,
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scanb_sen // bist scan shift enable
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extest ,
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tck
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`endif
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`endif
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);
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);
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// WISHBONE system signals
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// WISHBONE system signals
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input CLK_I ;
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input CLK_I ;
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| Line 272... |
Line 273... |
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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/*-----------------------------------------------------
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BIST debug chain port signals
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BIST debug chain port signals
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-----------------------------------------------------*/
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-----------------------------------------------------*/
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input trst ;
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input scanb_rst; // bist scan reset
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output SO ;
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input scanb_clk; // bist scan clock
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input SI ;
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input scanb_si; // bist scan serial in
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input shift_DR ;
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output scanb_so; // bist scan serial out
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input capture_DR ;
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input scanb_sen; // bist scan shift enable
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input extest ;
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input tck ;
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// internal wires for serial chain connection
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// internal wires for serial chain connection
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wire SO_internal ;
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wire SO_internal ;
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wire SI_internal = SO_internal ;
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wire SI_internal = SO_internal ;
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`endif
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`endif
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| Line 798... |
Line 797... |
.wbu_pciif_stop_reg_in (wbu_pciif_stop_reg_in),
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.wbu_pciif_stop_reg_in (wbu_pciif_stop_reg_in),
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.wbu_pciif_devsel_reg_in (wbu_pciif_devsel_reg_in)
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.wbu_pciif_devsel_reg_in (wbu_pciif_devsel_reg_in)
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|
|
`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.trst (trst),
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.scanb_rst (scanb_rst),
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.SO (SO_internal),
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.scanb_clk (scanb_clk),
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.SI (SI),
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.scanb_si (scanb_si),
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.shift_DR (shift_DR),
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.scanb_so (scanb_so),
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.capture_DR (capture_DR),
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.scanb_sen (scanb_sen)
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.extest (extest),
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.tck (tck)
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`endif
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`endif
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);
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);
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// PCI TARGET UNIT INPUTS
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// PCI TARGET UNIT INPUTS
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wire [31:0] pciu_mdata_in = MDAT_I ;
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wire [31:0] pciu_mdata_in = MDAT_I ;
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| Line 982... |
Line 979... |
.pciu_pci_drcomp_pending_out (pciu_pci_drcomp_pending_out),
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.pciu_pci_drcomp_pending_out (pciu_pci_drcomp_pending_out),
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.pciu_pciw_fifo_empty_out (pciu_pciw_fifo_empty_out)
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.pciu_pciw_fifo_empty_out (pciu_pciw_fifo_empty_out)
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|
|
`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.trst (trst),
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.scanb_rst (scanb_rst),
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.SO (SO),
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.scanb_clk (scanb_clk),
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.SI (SI_internal),
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.scanb_si (scanb_si),
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.shift_DR (shift_DR),
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.scanb_so (scanb_so),
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.capture_DR (capture_DR),
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.scanb_sen (scanb_sen)
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.extest (extest),
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.tck (tck)
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`endif
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`endif
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);
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);
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|
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// CONFIGURATION SPACE INPUTS
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// CONFIGURATION SPACE INPUTS
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