| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
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// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
|
|
// Revision 1.8 2002/10/21 13:04:33 mihad
|
|
// Changed BIST signal names etc..
|
|
//
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// Revision 1.7 2002/10/18 03:36:37 tadejm
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// Revision 1.7 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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// Changed wrong signal name scanb_sen into scanb_en.
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//
|
//
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// Revision 1.6 2002/10/17 22:51:50 tadejm
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// Revision 1.6 2002/10/17 22:51:50 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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| Line 74... |
Line 77... |
|
|
// this is top level module of pci bridge core
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// this is top level module of pci bridge core
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// it instantiates and connects other lower level modules
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// it instantiates and connects other lower level modules
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// check polarity of PCI output enables in file out_reg.v and change it according to IO interface specification
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// check polarity of PCI output enables in file out_reg.v and change it according to IO interface specification
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|
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module PCI_BRIDGE32
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module pci_bridge32
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(
|
(
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// WISHBONE system signals
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// WISHBONE system signals
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CLK_I,
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wb_clk_i,
|
RST_I,
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wb_rst_i,
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RST_O,
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wb_rst_o,
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INT_I,
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wb_int_i,
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INT_O,
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wb_int_o,
|
|
|
// WISHBONE slave interface
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// WISHBONE slave interface
|
ADR_I,
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wbs_adr_i,
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SDAT_I,
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wbs_dat_i,
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SDAT_O,
|
wbs_dat_o,
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SEL_I,
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wbs_sel_i,
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CYC_I,
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wbs_cyc_i,
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STB_I,
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wbs_stb_i,
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WE_I,
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wbs_we_i,
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CAB_I,
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wbs_cab_i,
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ACK_O,
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wbs_ack_o,
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RTY_O,
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wbs_rty_o,
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ERR_O,
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wbs_err_o,
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|
|
// WISHBONE master interface
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// WISHBONE master interface
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ADR_O,
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wbm_adr_o,
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MDAT_I,
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wbm_dat_i,
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MDAT_O,
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wbm_dat_o,
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SEL_O,
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wbm_sel_o,
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CYC_O,
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wbm_cyc_o,
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STB_O,
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wbm_stb_o,
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WE_O,
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wbm_we_o,
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CAB_O,
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wbm_cab_o,
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ACK_I,
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wbm_ack_i,
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RTY_I,
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wbm_rty_i,
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ERR_I,
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wbm_err_i,
|
|
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// pci interface - system pins
|
// pci interface - system pins
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PCI_CLK_IN,
|
pci_clk_i,
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PCI_RSTn_IN,
|
pci_rst_i,
|
PCI_RSTn_OUT,
|
pci_rst_o,
|
PCI_INTAn_IN,
|
pci_inta_i,
|
PCI_INTAn_OUT,
|
pci_inta_o,
|
PCI_RSTn_EN_OUT,
|
pci_rst_oe_o,
|
PCI_INTAn_EN_OUT,
|
pci_inta_oe_o,
|
|
|
// arbitration pins
|
// arbitration pins
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PCI_REQn_OUT,
|
pci_req_o,
|
PCI_REQn_EN_OUT,
|
pci_req_oe_o,
|
|
|
PCI_GNTn_IN,
|
pci_gnt_i,
|
|
|
// protocol pins
|
// protocol pins
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PCI_FRAMEn_IN,
|
pci_frame_i,
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PCI_FRAMEn_OUT,
|
pci_frame_o,
|
PCI_FRAMEn_EN_OUT,
|
|
PCI_IRDYn_EN_OUT,
|
pci_frame_oe_o,
|
PCI_DEVSELn_EN_OUT,
|
pci_irdy_oe_o,
|
PCI_TRDYn_EN_OUT,
|
pci_devsel_oe_o,
|
PCI_STOPn_EN_OUT,
|
pci_trdy_oe_o,
|
PCI_AD_EN_OUT,
|
pci_stop_oe_o,
|
PCI_CBEn_EN_OUT,
|
pci_ad_oe_o,
|
|
pci_cbe_oe_o,
|
PCI_IRDYn_IN,
|
|
PCI_IRDYn_OUT,
|
pci_irdy_i,
|
|
pci_irdy_o,
|
PCI_IDSEL_IN,
|
|
|
pci_idsel_i,
|
PCI_DEVSELn_IN,
|
|
PCI_DEVSELn_OUT,
|
|
|
|
|
pci_devsel_i,
|
|
pci_devsel_o,
|
|
|
PCI_TRDYn_IN,
|
pci_trdy_i,
|
PCI_TRDYn_OUT,
|
pci_trdy_o,
|
|
|
PCI_STOPn_IN,
|
pci_stop_i,
|
PCI_STOPn_OUT,
|
pci_stop_o ,
|
|
|
// data transfer pins
|
// data transfer pins
|
PCI_AD_IN,
|
pci_ad_i,
|
PCI_AD_OUT,
|
pci_ad_o,
|
|
|
PCI_CBEn_IN,
|
pci_cbe_i,
|
PCI_CBEn_OUT,
|
pci_cbe_o,
|
|
|
// parity generation and checking pins
|
// parity generation and checking pins
|
PCI_PAR_IN,
|
pci_par_i,
|
PCI_PAR_OUT,
|
pci_par_o,
|
PCI_PAR_EN_OUT,
|
pci_par_oe_o,
|
|
|
PCI_PERRn_IN,
|
pci_perr_i,
|
PCI_PERRn_OUT,
|
pci_perr_o,
|
PCI_PERRn_EN_OUT,
|
pci_perr_oe_o,
|
|
|
// system error pin
|
// system error pin
|
PCI_SERRn_OUT,
|
pci_serr_o,
|
PCI_SERRn_EN_OUT
|
pci_serr_oe_o
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
,
|
,
|
// debug chain signals
|
// debug chain signals
|
scanb_rst, // bist scan reset
|
scanb_rst, // bist scan reset
|
| Line 182... |
Line 185... |
scanb_en // bist scan shift enable
|
scanb_en // bist scan shift enable
|
`endif
|
`endif
|
);
|
);
|
|
|
// WISHBONE system signals
|
// WISHBONE system signals
|
input CLK_I ;
|
input wb_clk_i ;
|
input RST_I ;
|
input wb_rst_i ;
|
output RST_O ;
|
output wb_rst_o ;
|
input INT_I ;
|
input wb_int_i ;
|
output INT_O ;
|
output wb_int_o ;
|
|
|
// WISHBONE slave interface
|
// WISHBONE slave interface
|
input [31:0] ADR_I ;
|
input [31:0] wbs_adr_i ;
|
input [31:0] SDAT_I ;
|
input [31:0] wbs_dat_i ;
|
output [31:0] SDAT_O ;
|
output [31:0] wbs_dat_o ;
|
input [3:0] SEL_I ;
|
input [3:0] wbs_sel_i ;
|
input CYC_I ;
|
input wbs_cyc_i ;
|
input STB_I ;
|
input wbs_stb_i ;
|
input WE_I ;
|
input wbs_we_i ;
|
input CAB_I ;
|
input wbs_cab_i ;
|
output ACK_O ;
|
output wbs_ack_o ;
|
output RTY_O ;
|
output wbs_rty_o ;
|
output ERR_O ;
|
output wbs_err_o ;
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
output [31:0] ADR_O ;
|
output [31:0] wbm_adr_o ;
|
input [31:0] MDAT_I ;
|
input [31:0] wbm_dat_i ;
|
output [31:0] MDAT_O ;
|
output [31:0] wbm_dat_o ;
|
output [3:0] SEL_O ;
|
output [3:0] wbm_sel_o ;
|
output CYC_O ;
|
output wbm_cyc_o ;
|
output STB_O ;
|
output wbm_stb_o ;
|
output WE_O ;
|
output wbm_we_o ;
|
output CAB_O ;
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output wbm_cab_o ;
|
input ACK_I ;
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input wbm_ack_i ;
|
input RTY_I ;
|
input wbm_rty_i ;
|
input ERR_I ;
|
input wbm_err_i ;
|
|
|
// pci interface - system pins
|
// pci interface - system pins
|
input PCI_CLK_IN ;
|
input pci_clk_i ;
|
input PCI_RSTn_IN ;
|
input pci_rst_i ;
|
output PCI_RSTn_OUT ;
|
output pci_rst_o ;
|
output PCI_RSTn_EN_OUT ;
|
output pci_rst_oe_o ;
|
|
|
input PCI_INTAn_IN ;
|
input pci_inta_i ;
|
output PCI_INTAn_OUT ;
|
output pci_inta_o ;
|
output PCI_INTAn_EN_OUT ;
|
output pci_inta_oe_o ;
|
|
|
// arbitration pins
|
// arbitration pins
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output PCI_REQn_OUT ;
|
output pci_req_o ;
|
output PCI_REQn_EN_OUT ;
|
output pci_req_oe_o ;
|
|
|
input PCI_GNTn_IN ;
|
input pci_gnt_i ;
|
|
|
// protocol pins
|
// protocol pins
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input PCI_FRAMEn_IN ;
|
input pci_frame_i ;
|
output PCI_FRAMEn_OUT ;
|
output pci_frame_o ;
|
output PCI_FRAMEn_EN_OUT ;
|
output pci_frame_oe_o ;
|
output PCI_IRDYn_EN_OUT ;
|
output pci_irdy_oe_o ;
|
output PCI_DEVSELn_EN_OUT ;
|
output pci_devsel_oe_o ;
|
output PCI_TRDYn_EN_OUT ;
|
output pci_trdy_oe_o ;
|
output PCI_STOPn_EN_OUT ;
|
output pci_stop_oe_o ;
|
output [31:0] PCI_AD_EN_OUT ;
|
output [31:0] pci_ad_oe_o ;
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output [3:0] PCI_CBEn_EN_OUT ;
|
output [3:0] pci_cbe_oe_o ;
|
|
|
input PCI_IRDYn_IN ;
|
input pci_irdy_i ;
|
output PCI_IRDYn_OUT ;
|
output pci_irdy_o ;
|
|
|
input PCI_IDSEL_IN ;
|
input pci_idsel_i ;
|
|
|
input PCI_DEVSELn_IN ;
|
input pci_devsel_i ;
|
output PCI_DEVSELn_OUT ;
|
output pci_devsel_o ;
|
|
|
input PCI_TRDYn_IN ;
|
input pci_trdy_i ;
|
output PCI_TRDYn_OUT ;
|
output pci_trdy_o ;
|
|
|
input PCI_STOPn_IN ;
|
input pci_stop_i ;
|
output PCI_STOPn_OUT ;
|
output pci_stop_o ;
|
|
|
// data transfer pins
|
// data transfer pins
|
input [31:0] PCI_AD_IN ;
|
input [31:0] pci_ad_i ;
|
output [31:0] PCI_AD_OUT ;
|
output [31:0] pci_ad_o ;
|
|
|
input [3:0] PCI_CBEn_IN ;
|
input [3:0] pci_cbe_i ;
|
output [3:0] PCI_CBEn_OUT ;
|
output [3:0] pci_cbe_o ;
|
|
|
// parity generation and checking pins
|
// parity generation and checking pins
|
input PCI_PAR_IN ;
|
input pci_par_i ;
|
output PCI_PAR_OUT ;
|
output pci_par_o ;
|
output PCI_PAR_EN_OUT ;
|
output pci_par_oe_o ;
|
|
|
input PCI_PERRn_IN ;
|
input pci_perr_i ;
|
output PCI_PERRn_OUT ;
|
output pci_perr_o ;
|
output PCI_PERRn_EN_OUT ;
|
output pci_perr_oe_o ;
|
|
|
// system error pin
|
// system error pin
|
output PCI_SERRn_OUT ;
|
output pci_serr_o ;
|
output PCI_SERRn_EN_OUT ;
|
output pci_serr_oe_o ;
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
/*-----------------------------------------------------
|
/*-----------------------------------------------------
|
BIST debug chain port signals
|
BIST debug chain port signals
|
-----------------------------------------------------*/
|
-----------------------------------------------------*/
|
| Line 291... |
Line 294... |
wire SO_internal ;
|
wire SO_internal ;
|
wire SI_internal = SO_internal ;
|
wire SI_internal = SO_internal ;
|
`endif
|
`endif
|
|
|
// declare clock and reset wires
|
// declare clock and reset wires
|
wire pci_clk = PCI_CLK_IN ;
|
wire pci_clk = pci_clk_i ;
|
wire wb_clk = CLK_I ;
|
wire wb_clk = wb_clk_i ;
|
wire reset ; // assigned at pci bridge reset and interrupt logic
|
wire reset ; // assigned at pci bridge reset and interrupt logic
|
|
|
/*=========================================================================================================
|
/*=========================================================================================================
|
First comes definition of all modules' outputs, so they can be assigned to any other module's input later
|
First comes definition of all modules' outputs, so they can be assigned to any other module's input later
|
in the file, when module is instantiated
|
in the file, when module is instantiated
|
| Line 311... |
Line 314... |
wire pci_into_int_o ;
|
wire pci_into_int_o ;
|
wire pci_into_conf_isr_int_prop_out ;
|
wire pci_into_conf_isr_int_prop_out ;
|
|
|
// assign pci bridge reset interrupt logic outputs to top outputs where possible
|
// assign pci bridge reset interrupt logic outputs to top outputs where possible
|
assign reset = pci_reso_reset ;
|
assign reset = pci_reso_reset ;
|
assign PCI_RSTn_OUT = pci_reso_pci_rstn_out ;
|
assign pci_rst_o = pci_reso_pci_rstn_out ;
|
assign PCI_RSTn_EN_OUT = pci_reso_pci_rstn_en_out ;
|
assign pci_rst_oe_o = pci_reso_pci_rstn_en_out ;
|
assign RST_O = pci_reso_rst_o ;
|
assign wb_rst_o = pci_reso_rst_o ;
|
assign PCI_INTAn_OUT = pci_into_pci_intan_out ;
|
assign pci_inta_o = pci_into_pci_intan_out ;
|
assign PCI_INTAn_EN_OUT = pci_into_pci_intan_en_out ;
|
assign pci_inta_oe_o = pci_into_pci_intan_en_out ;
|
assign INT_O = pci_into_int_o ;
|
assign wb_int_o = pci_into_int_o ;
|
|
|
// WISHBONE SLAVE UNIT OUTPUTS
|
// WISHBONE SLAVE UNIT OUTPUTS
|
wire [31:0] wbu_sdata_out ;
|
wire [31:0] wbu_sdata_out ;
|
wire wbu_ack_out ;
|
wire wbu_ack_out ;
|
wire wbu_rty_out ;
|
wire wbu_rty_out ;
|
| Line 351... |
Line 354... |
wire wbu_ad_load_out ;
|
wire wbu_ad_load_out ;
|
wire wbu_ad_load_on_transfer_out ;
|
wire wbu_ad_load_on_transfer_out ;
|
wire wbu_pciif_frame_load_out ;
|
wire wbu_pciif_frame_load_out ;
|
|
|
// assign wishbone slave unit's outputs to top outputs where possible
|
// assign wishbone slave unit's outputs to top outputs where possible
|
assign SDAT_O = wbu_sdata_out ;
|
assign wbs_dat_o = wbu_sdata_out ;
|
assign ACK_O = wbu_ack_out ;
|
assign wbs_ack_o = wbu_ack_out ;
|
assign RTY_O = wbu_rty_out ;
|
assign wbs_rty_o = wbu_rty_out ;
|
assign ERR_O = wbu_err_out ;
|
assign wbs_err_o = wbu_err_out ;
|
|
|
// PCI TARGET UNIT OUTPUTS
|
// PCI TARGET UNIT OUTPUTS
|
wire [31:0] pciu_adr_out ;
|
wire [31:0] pciu_adr_out ;
|
wire [31:0] pciu_mdata_out ;
|
wire [31:0] pciu_mdata_out ;
|
wire pciu_cyc_out ;
|
wire pciu_cyc_out ;
|
| Line 392... |
Line 395... |
wire [31:0] pciu_conf_data_out ;
|
wire [31:0] pciu_conf_data_out ;
|
wire pciu_pci_drcomp_pending_out ;
|
wire pciu_pci_drcomp_pending_out ;
|
wire pciu_pciw_fifo_empty_out ;
|
wire pciu_pciw_fifo_empty_out ;
|
|
|
// assign pci target unit's outputs to top outputs where possible
|
// assign pci target unit's outputs to top outputs where possible
|
assign ADR_O = pciu_adr_out ;
|
assign wbm_adr_o = pciu_adr_out ;
|
assign MDAT_O = pciu_mdata_out ;
|
assign wbm_dat_o = pciu_mdata_out ;
|
assign CYC_O = pciu_cyc_out ;
|
assign wbm_cyc_o = pciu_cyc_out ;
|
assign STB_O = pciu_stb_out ;
|
assign wbm_stb_o = pciu_stb_out ;
|
assign WE_O = pciu_we_out ;
|
assign wbm_we_o = pciu_we_out ;
|
assign SEL_O = pciu_sel_out ;
|
assign wbm_sel_o = pciu_sel_out ;
|
assign CAB_O = pciu_cab_out ;
|
assign wbm_cab_o = pciu_cab_out ;
|
|
|
// CONFIGURATION SPACE OUTPUTS
|
// CONFIGURATION SPACE OUTPUTS
|
wire [31:0] conf_w_data_out ;
|
wire [31:0] conf_w_data_out ;
|
wire [31:0] conf_r_data_out ;
|
wire [31:0] conf_r_data_out ;
|
wire conf_serr_enable_out ;
|
wire conf_serr_enable_out ;
|
| Line 513... |
Line 516... |
wire pci_mux_req_out ;
|
wire pci_mux_req_out ;
|
wire pci_mux_req_en_out ;
|
wire pci_mux_req_en_out ;
|
|
|
// assign outputs to top level outputs
|
// assign outputs to top level outputs
|
|
|
assign PCI_AD_EN_OUT = pci_mux_ad_en_out ;
|
assign pci_ad_oe_o = pci_mux_ad_en_out ;
|
assign PCI_FRAMEn_EN_OUT = pci_mux_frame_en_out ;
|
assign pci_frame_oe_o = pci_mux_frame_en_out ;
|
assign PCI_IRDYn_EN_OUT = pci_mux_irdy_en_out ;
|
assign pci_irdy_oe_o = pci_mux_irdy_en_out ;
|
assign PCI_CBEn_EN_OUT = pci_mux_cbe_en_out ;
|
assign pci_cbe_oe_o = pci_mux_cbe_en_out ;
|
|
|
assign PCI_PAR_OUT = pci_mux_par_out ;
|
assign pci_par_o = pci_mux_par_out ;
|
assign PCI_PAR_EN_OUT = pci_mux_par_en_out ;
|
assign pci_par_oe_o = pci_mux_par_en_out ;
|
assign PCI_PERRn_OUT = pci_mux_perr_out ;
|
assign pci_perr_o = pci_mux_perr_out ;
|
assign PCI_PERRn_EN_OUT = pci_mux_perr_en_out ;
|
assign pci_perr_oe_o = pci_mux_perr_en_out ;
|
assign PCI_SERRn_OUT = pci_mux_serr_out ;
|
assign pci_serr_o = pci_mux_serr_out ;
|
assign PCI_SERRn_EN_OUT = pci_mux_serr_en_out ;
|
assign pci_serr_oe_o = pci_mux_serr_en_out ;
|
|
|
assign PCI_REQn_OUT = pci_mux_req_out ;
|
assign pci_req_o = pci_mux_req_out ;
|
assign PCI_REQn_EN_OUT = pci_mux_req_en_out ;
|
assign pci_req_oe_o = pci_mux_req_en_out ;
|
|
|
assign PCI_TRDYn_EN_OUT = pci_mux_trdy_en_out ;
|
assign pci_trdy_oe_o = pci_mux_trdy_en_out ;
|
assign PCI_DEVSELn_EN_OUT = pci_mux_devsel_en_out ;
|
assign pci_devsel_oe_o = pci_mux_devsel_en_out ;
|
assign PCI_STOPn_EN_OUT = pci_mux_stop_en_out ;
|
assign pci_stop_oe_o = pci_mux_stop_en_out ;
|
assign PCI_TRDYn_OUT = pci_mux_trdy_out ;
|
assign pci_trdy_o = pci_mux_trdy_out ;
|
assign PCI_DEVSELn_OUT = pci_mux_devsel_out ;
|
assign pci_devsel_o = pci_mux_devsel_out ;
|
assign PCI_STOPn_OUT = pci_mux_stop_out ;
|
assign pci_stop_o = pci_mux_stop_out ;
|
|
|
assign PCI_AD_OUT = pci_mux_ad_out ;
|
assign pci_ad_o = pci_mux_ad_out ;
|
assign PCI_FRAMEn_OUT = pci_mux_frame_out ;
|
assign pci_frame_o = pci_mux_frame_out ;
|
assign PCI_IRDYn_OUT = pci_mux_irdy_out ;
|
assign pci_irdy_o = pci_mux_irdy_out ;
|
assign PCI_CBEn_OUT = pci_mux_cbe_out ;
|
assign pci_cbe_o = pci_mux_cbe_out ;
|
|
|
// duplicate output register's outputs
|
// duplicate output register's outputs
|
wire out_bckp_frame_out ;
|
wire out_bckp_frame_out ;
|
wire out_bckp_irdy_out ;
|
wire out_bckp_irdy_out ;
|
wire out_bckp_devsel_out ;
|
wire out_bckp_devsel_out ;
|
| Line 590... |
Line 593... |
|
|
/*=========================================================================================================
|
/*=========================================================================================================
|
Now comes definition of all modules' and their appropriate inputs
|
Now comes definition of all modules' and their appropriate inputs
|
=========================================================================================================*/
|
=========================================================================================================*/
|
// PCI BRIDGE RESET AND INTERRUPT LOGIC INPUTS
|
// PCI BRIDGE RESET AND INTERRUPT LOGIC INPUTS
|
wire pci_resi_rst_i = RST_I ;
|
wire pci_resi_rst_i = wb_rst_i ;
|
wire pci_resi_pci_rstn_in = PCI_RSTn_IN ;
|
wire pci_resi_pci_rstn_in = pci_rst_i ;
|
wire pci_resi_conf_soft_res_in = conf_soft_res_out ;
|
wire pci_resi_conf_soft_res_in = conf_soft_res_out ;
|
wire pci_inti_pci_intan_in = PCI_INTAn_IN ;
|
wire pci_inti_pci_intan_in = pci_inta_i ;
|
wire pci_inti_conf_int_in = conf_int_out ;
|
wire pci_inti_conf_int_in = conf_int_out ;
|
wire pci_inti_int_i = INT_I ;
|
wire pci_inti_int_i = wb_int_i ;
|
wire pci_inti_out_bckp_perr_en_in = out_bckp_perr_en_out ;
|
wire pci_inti_out_bckp_perr_en_in = out_bckp_perr_en_out ;
|
wire pci_inti_out_bckp_serr_en_in = out_bckp_serr_en_out ;
|
wire pci_inti_out_bckp_serr_en_in = out_bckp_serr_en_out ;
|
|
|
PCI_RST_INT pci_resets_and_interrupts
|
pci_rst_int pci_resets_and_interrupts
|
(
|
(
|
.clk_in (pci_clk),
|
.clk_in (pci_clk),
|
.rst_i (pci_resi_rst_i),
|
.rst_i (pci_resi_rst_i),
|
.pci_rstn_in (pci_resi_pci_rstn_in),
|
.pci_rstn_in (pci_resi_pci_rstn_in),
|
.conf_soft_res_in (pci_resi_conf_soft_res_in),
|
.conf_soft_res_in (pci_resi_conf_soft_res_in),
|
| Line 621... |
Line 624... |
.int_o (pci_into_int_o),
|
.int_o (pci_into_int_o),
|
.conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out)
|
.conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out)
|
);
|
);
|
|
|
// WISHBONE SLAVE UNIT INPUTS
|
// WISHBONE SLAVE UNIT INPUTS
|
wire [31:0] wbu_addr_in = ADR_I ;
|
wire [31:0] wbu_addr_in = wbs_adr_i ;
|
wire [31:0] wbu_sdata_in = SDAT_I ;
|
wire [31:0] wbu_sdata_in = wbs_dat_i ;
|
wire wbu_cyc_in = CYC_I ;
|
wire wbu_cyc_in = wbs_cyc_i ;
|
wire wbu_stb_in = STB_I ;
|
wire wbu_stb_in = wbs_stb_i ;
|
wire wbu_we_in = WE_I ;
|
wire wbu_we_in = wbs_we_i ;
|
wire [3:0] wbu_sel_in = SEL_I ;
|
wire [3:0] wbu_sel_in = wbs_sel_i ;
|
wire wbu_cab_in = CAB_I ;
|
wire wbu_cab_in = wbs_cab_i ;
|
|
|
wire [5:0] wbu_map_in = {
|
wire [5:0] wbu_map_in = {
|
conf_wb_mem_io5_out,
|
conf_wb_mem_io5_out,
|
conf_wb_mem_io4_out,
|
conf_wb_mem_io4_out,
|
conf_wb_mem_io3_out,
|
conf_wb_mem_io3_out,
|
| Line 699... |
Line 702... |
wire [23:0] wbu_ccyc_addr_in = conf_ccyc_addr_out ;
|
wire [23:0] wbu_ccyc_addr_in = conf_ccyc_addr_out ;
|
wire wbu_master_enable_in = conf_pci_master_enable_out ;
|
wire wbu_master_enable_in = conf_pci_master_enable_out ;
|
wire wbu_cache_line_size_not_zero = conf_cache_lsize_not_zero_to_wb_out ;
|
wire wbu_cache_line_size_not_zero = conf_cache_lsize_not_zero_to_wb_out ;
|
wire [7:0] wbu_cache_line_size_in = conf_cache_line_size_to_pci_out ;
|
wire [7:0] wbu_cache_line_size_in = conf_cache_line_size_to_pci_out ;
|
|
|
wire wbu_pciif_gnt_in = PCI_GNTn_IN ;
|
wire wbu_pciif_gnt_in = pci_gnt_i ;
|
wire wbu_pciif_frame_in = in_reg_frame_out ;
|
wire wbu_pciif_frame_in = in_reg_frame_out ;
|
wire wbu_pciif_irdy_in = in_reg_irdy_out ;
|
wire wbu_pciif_irdy_in = in_reg_irdy_out ;
|
wire wbu_pciif_trdy_in = PCI_TRDYn_IN ;
|
wire wbu_pciif_trdy_in = pci_trdy_i ;
|
wire wbu_pciif_stop_in = PCI_STOPn_IN ;
|
wire wbu_pciif_stop_in = pci_stop_i ;
|
wire wbu_pciif_devsel_in = PCI_DEVSELn_IN ;
|
wire wbu_pciif_devsel_in = pci_devsel_i ;
|
wire [31:0] wbu_pciif_ad_reg_in = in_reg_ad_out ;
|
wire [31:0] wbu_pciif_ad_reg_in = in_reg_ad_out ;
|
wire wbu_pciif_trdy_reg_in = in_reg_trdy_out ;
|
wire wbu_pciif_trdy_reg_in = in_reg_trdy_out ;
|
wire wbu_pciif_stop_reg_in = in_reg_stop_out ;
|
wire wbu_pciif_stop_reg_in = in_reg_stop_out ;
|
wire wbu_pciif_devsel_reg_in = in_reg_devsel_out ;
|
wire wbu_pciif_devsel_reg_in = in_reg_devsel_out ;
|
|
|
| Line 716... |
Line 719... |
wire [7:0] wbu_latency_tim_val_in = conf_latency_tim_out ;
|
wire [7:0] wbu_latency_tim_val_in = conf_latency_tim_out ;
|
|
|
wire wbu_pciif_frame_en_in = out_bckp_frame_en_out ;
|
wire wbu_pciif_frame_en_in = out_bckp_frame_en_out ;
|
wire wbu_pciif_frame_out_in = out_bckp_frame_out ;
|
wire wbu_pciif_frame_out_in = out_bckp_frame_out ;
|
|
|
WB_SLAVE_UNIT wishbone_slave_unit
|
pci_wb_slave_unit wishbone_slave_unit
|
(
|
(
|
.reset_in (reset),
|
.reset_in (reset),
|
.wb_clock_in (wb_clk),
|
.wb_clock_in (wb_clk),
|
.pci_clock_in (pci_clk),
|
.pci_clock_in (pci_clk),
|
.ADDR_I (wbu_addr_in),
|
.ADDR_I (wbu_addr_in),
|
| Line 812... |
Line 815... |
.scanb_en (scanb_en)
|
.scanb_en (scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
// PCI TARGET UNIT INPUTS
|
// PCI TARGET UNIT INPUTS
|
wire [31:0] pciu_mdata_in = MDAT_I ;
|
wire [31:0] pciu_mdata_in = wbm_dat_i ;
|
wire pciu_ack_in = ACK_I ;
|
wire pciu_ack_in = wbm_ack_i ;
|
wire pciu_rty_in = RTY_I ;
|
wire pciu_rty_in = wbm_rty_i ;
|
wire pciu_err_in = ERR_I ;
|
wire pciu_err_in = wbm_err_i ;
|
|
|
wire [5:0] pciu_map_in = {
|
wire [5:0] pciu_map_in = {
|
conf_pci_mem_io5_out,
|
conf_pci_mem_io5_out,
|
conf_pci_mem_io4_out,
|
conf_pci_mem_io4_out,
|
conf_pci_mem_io3_out,
|
conf_pci_mem_io3_out,
|
| Line 881... |
Line 884... |
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta5_in = conf_pci_ta5_out ;
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta5_in = conf_pci_ta5_out ;
|
|
|
wire [7:0] pciu_cache_line_size_in = conf_cache_line_size_to_wb_out ;
|
wire [7:0] pciu_cache_line_size_in = conf_cache_line_size_to_wb_out ;
|
wire pciu_cache_lsize_not_zero_in = conf_cache_lsize_not_zero_to_wb_out ;
|
wire pciu_cache_lsize_not_zero_in = conf_cache_lsize_not_zero_to_wb_out ;
|
|
|
wire pciu_pciif_frame_in = PCI_FRAMEn_IN ;
|
wire pciu_pciif_frame_in = pci_frame_i ;
|
wire pciu_pciif_irdy_in = PCI_IRDYn_IN ;
|
wire pciu_pciif_irdy_in = pci_irdy_i ;
|
wire pciu_pciif_idsel_in = PCI_IDSEL_IN ;
|
wire pciu_pciif_idsel_in = pci_idsel_i ;
|
wire pciu_pciif_frame_reg_in = in_reg_frame_out ;
|
wire pciu_pciif_frame_reg_in = in_reg_frame_out ;
|
wire pciu_pciif_irdy_reg_in = in_reg_irdy_out ;
|
wire pciu_pciif_irdy_reg_in = in_reg_irdy_out ;
|
wire pciu_pciif_idsel_reg_in = in_reg_idsel_out ;
|
wire pciu_pciif_idsel_reg_in = in_reg_idsel_out ;
|
wire [31:0] pciu_pciif_ad_reg_in = in_reg_ad_out ;
|
wire [31:0] pciu_pciif_ad_reg_in = in_reg_ad_out ;
|
wire [3:0] pciu_pciif_cbe_reg_in = in_reg_cbe_out ;
|
wire [3:0] pciu_pciif_cbe_reg_in = in_reg_cbe_out ;
|
| Line 897... |
Line 900... |
wire pciu_pciif_bckp_trdy_in = out_bckp_trdy_out ;
|
wire pciu_pciif_bckp_trdy_in = out_bckp_trdy_out ;
|
wire pciu_pciif_bckp_stop_in = out_bckp_stop_out ;
|
wire pciu_pciif_bckp_stop_in = out_bckp_stop_out ;
|
wire pciu_pciif_trdy_reg_in = in_reg_trdy_out ;
|
wire pciu_pciif_trdy_reg_in = in_reg_trdy_out ;
|
wire pciu_pciif_stop_reg_in = in_reg_stop_out ;
|
wire pciu_pciif_stop_reg_in = in_reg_stop_out ;
|
|
|
PCI_TARGET_UNIT pci_target_unit
|
pci_target_unit pci_target_unit
|
(
|
(
|
.reset_in (reset),
|
.reset_in (reset),
|
.wb_clock_in (wb_clk),
|
.wb_clock_in (wb_clk),
|
.pci_clock_in (pci_clk),
|
.pci_clock_in (pci_clk),
|
.ADR_O (pciu_adr_out),
|
.ADR_O (pciu_adr_out),
|
| Line 1050... |
Line 1053... |
|
|
wire conf_isr_int_prop_in = pci_into_conf_isr_int_prop_out ;
|
wire conf_isr_int_prop_in = pci_into_conf_isr_int_prop_out ;
|
wire conf_par_err_int_in = parchk_perr_mas_detect_out ;
|
wire conf_par_err_int_in = parchk_perr_mas_detect_out ;
|
wire conf_sys_err_int_in = parchk_sig_serr_out ;
|
wire conf_sys_err_int_in = parchk_sig_serr_out ;
|
|
|
CONF_SPACE configuration (
|
pci_conf_space configuration(
|
.reset (reset),
|
.reset (reset),
|
.pci_clk (pci_clk),
|
.pci_clk (pci_clk),
|
.wb_clk (wb_clk),
|
.wb_clk (wb_clk),
|
.w_conf_address_in (conf_w_addr_in),
|
.w_conf_address_in (conf_w_addr_in),
|
.w_conf_data_in (conf_w_data_in),
|
.w_conf_data_in (conf_w_data_in),
|
| Line 1196... |
Line 1199... |
wire pci_mux_serr_en_in = parchk_pci_serr_en_out;
|
wire pci_mux_serr_en_in = parchk_pci_serr_en_out;
|
|
|
wire pci_mux_req_in = wbu_pciif_req_out ;
|
wire pci_mux_req_in = wbu_pciif_req_out ;
|
wire pci_mux_frame_load_in = wbu_pciif_frame_load_out ;
|
wire pci_mux_frame_load_in = wbu_pciif_frame_load_out ;
|
|
|
wire pci_mux_pci_irdy_in = PCI_IRDYn_IN ;
|
wire pci_mux_pci_irdy_in = pci_irdy_i ;
|
wire pci_mux_pci_trdy_in = PCI_TRDYn_IN ;
|
wire pci_mux_pci_trdy_in = pci_trdy_i ;
|
wire pci_mux_pci_frame_in = PCI_FRAMEn_IN ;
|
wire pci_mux_pci_frame_in = pci_frame_i ;
|
wire pci_mux_pci_stop_in = PCI_STOPn_IN ;
|
wire pci_mux_pci_stop_in = pci_stop_i ;
|
|
|
PCI_IO_MUX pci_io_mux
|
pci_io_mux pci_io_mux
|
(
|
(
|
.reset_in (reset),
|
.reset_in (reset),
|
.clk_in (pci_clk),
|
.clk_in (pci_clk),
|
.frame_in (pci_mux_frame_in),
|
.frame_in (pci_mux_frame_in),
|
.frame_en_in (pci_mux_frame_en_in),
|
.frame_en_in (pci_mux_frame_en_in),
|
| Line 1269... |
Line 1272... |
.pci_frame_in (pci_mux_pci_frame_in),
|
.pci_frame_in (pci_mux_pci_frame_in),
|
.pci_stop_in (pci_mux_pci_stop_in),
|
.pci_stop_in (pci_mux_pci_stop_in),
|
.ad_en_unregistered_out (pci_mux_ad_en_unregistered_out)
|
.ad_en_unregistered_out (pci_mux_ad_en_unregistered_out)
|
);
|
);
|
|
|
CUR_OUT_REG output_backup
|
pci_cur_out_reg output_backup
|
(
|
(
|
.reset_in (reset),
|
.reset_in (reset),
|
.clk_in (pci_clk),
|
.clk_in (pci_clk),
|
.frame_in (pci_mux_frame_in),
|
.frame_in (pci_mux_frame_in),
|
.frame_en_in (pci_mux_frame_en_in),
|
.frame_en_in (pci_mux_frame_en_in),
|
| Line 1323... |
Line 1326... |
.serr_out (out_bckp_serr_out),
|
.serr_out (out_bckp_serr_out),
|
.serr_en_out (out_bckp_serr_en_out)
|
.serr_en_out (out_bckp_serr_en_out)
|
) ;
|
) ;
|
|
|
// PARITY CHECKER INPUTS
|
// PARITY CHECKER INPUTS
|
wire parchk_pci_par_in = PCI_PAR_IN ;
|
wire parchk_pci_par_in = pci_par_i ;
|
wire parchk_pci_perr_in = PCI_PERRn_IN ;
|
wire parchk_pci_perr_in = pci_perr_i ;
|
wire parchk_pci_frame_reg_in = in_reg_frame_out ;
|
wire parchk_pci_frame_reg_in = in_reg_frame_out ;
|
wire parchk_pci_frame_en_in = out_bckp_frame_en_out ;
|
wire parchk_pci_frame_en_in = out_bckp_frame_en_out ;
|
wire parchk_pci_irdy_en_in = out_bckp_irdy_en_out ;
|
wire parchk_pci_irdy_en_in = out_bckp_irdy_en_out ;
|
wire parchk_pci_irdy_reg_in = in_reg_irdy_out ;
|
wire parchk_pci_irdy_reg_in = in_reg_irdy_out ;
|
wire parchk_pci_trdy_reg_in = in_reg_trdy_out ;
|
wire parchk_pci_trdy_reg_in = in_reg_trdy_out ;
|
| Line 1337... |
Line 1340... |
wire parchk_pci_trdy_en_in = out_bckp_trdy_en_out ;
|
wire parchk_pci_trdy_en_in = out_bckp_trdy_en_out ;
|
|
|
|
|
wire [31:0] parchk_pci_ad_out_in = out_bckp_ad_out ;
|
wire [31:0] parchk_pci_ad_out_in = out_bckp_ad_out ;
|
wire [31:0] parchk_pci_ad_reg_in = in_reg_ad_out ;
|
wire [31:0] parchk_pci_ad_reg_in = in_reg_ad_out ;
|
wire [3:0] parchk_pci_cbe_in_in = PCI_CBEn_IN ;
|
wire [3:0] parchk_pci_cbe_in_in = pci_cbe_i ;
|
wire [3:0] parchk_pci_cbe_reg_in = in_reg_cbe_out ;
|
wire [3:0] parchk_pci_cbe_reg_in = in_reg_cbe_out ;
|
wire [3:0] parchk_pci_cbe_out_in = out_bckp_cbe_out ;
|
wire [3:0] parchk_pci_cbe_out_in = out_bckp_cbe_out ;
|
wire parchk_pci_ad_en_in = out_bckp_ad_en_out ;
|
wire parchk_pci_ad_en_in = out_bckp_ad_en_out ;
|
wire parchk_par_err_response_in = conf_perr_response_out ;
|
wire parchk_par_err_response_in = conf_perr_response_out ;
|
wire parchk_serr_enable_in = conf_serr_enable_out ;
|
wire parchk_serr_enable_in = conf_serr_enable_out ;
|
| Line 1351... |
Line 1354... |
wire parchk_pci_serr_out_in = out_bckp_serr_out ;
|
wire parchk_pci_serr_out_in = out_bckp_serr_out ;
|
wire parchk_pci_cbe_en_in = out_bckp_cbe_en_out ;
|
wire parchk_pci_cbe_en_in = out_bckp_cbe_en_out ;
|
|
|
wire parchk_pci_par_en_in = out_bckp_par_en_out ;
|
wire parchk_pci_par_en_in = out_bckp_par_en_out ;
|
|
|
PCI_PARITY_CHECK parity_checker
|
pci_parity_check parity_checker
|
(
|
(
|
.reset_in (reset),
|
.reset_in (reset),
|
.clk_in (pci_clk),
|
.clk_in (pci_clk),
|
.pci_par_in (parchk_pci_par_in),
|
.pci_par_in (parchk_pci_par_in),
|
.pci_par_out (parchk_pci_par_out),
|
.pci_par_out (parchk_pci_par_out),
|
| Line 1387... |
Line 1390... |
.perr_mas_detect_out (parchk_perr_mas_detect_out),
|
.perr_mas_detect_out (parchk_perr_mas_detect_out),
|
.serr_enable_in (parchk_serr_enable_in),
|
.serr_enable_in (parchk_serr_enable_in),
|
.sig_serr_out (parchk_sig_serr_out)
|
.sig_serr_out (parchk_sig_serr_out)
|
);
|
);
|
|
|
wire in_reg_gnt_in = PCI_GNTn_IN ;
|
wire in_reg_gnt_in = pci_gnt_i ;
|
wire in_reg_frame_in = PCI_FRAMEn_IN ;
|
wire in_reg_frame_in = pci_frame_i ;
|
wire in_reg_irdy_in = PCI_IRDYn_IN ;
|
wire in_reg_irdy_in = pci_irdy_i ;
|
wire in_reg_trdy_in = PCI_TRDYn_IN ;
|
wire in_reg_trdy_in = pci_trdy_i ;
|
wire in_reg_stop_in = PCI_STOPn_IN ;
|
wire in_reg_stop_in = pci_stop_i ;
|
wire in_reg_devsel_in = PCI_DEVSELn_IN ;
|
wire in_reg_devsel_in = pci_devsel_i ;
|
wire in_reg_idsel_in = PCI_IDSEL_IN ;
|
wire in_reg_idsel_in = pci_idsel_i ;
|
wire [31:0] in_reg_ad_in = PCI_AD_IN ;
|
wire [31:0] in_reg_ad_in = pci_ad_i ;
|
wire [3:0] in_reg_cbe_in = PCI_CBEn_IN ;
|
wire [3:0] in_reg_cbe_in = pci_cbe_i ;
|
|
|
PCI_IN_REG input_register
|
pci_in_reg input_register
|
(
|
(
|
.reset_in (reset),
|
.reset_in (reset),
|
.clk_in (pci_clk),
|
.clk_in (pci_clk),
|
|
|
.pci_gnt_in (in_reg_gnt_in),
|
.pci_gnt_in (in_reg_gnt_in),
|
