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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_delayed_sync.v] - Diff between revs 88 and 111

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Rev 88 Rev 111
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.2  2003/03/26 13:16:18  mihad
 
// Added the reset value parameter to the synchronizer flop module.
 
// Added resets to all synchronizer flop instances.
 
// Repaired initial sync value in fifos.
 
//
// Revision 1.1  2003/01/27 16:49:31  mihad
// Revision 1.1  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
//
// Revision 1.5  2002/09/25 09:54:50  mihad
// Revision 1.5  2002/09/25 09:54:50  mihad
// Added completion expiration test for WB Slave unit. Changed expiration signalling
// Added completion expiration test for WB Slave unit. Changed expiration signalling
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        req_req_pending <= #`FF_DELAY 1'b1 ;
        req_req_pending <= #`FF_DELAY 1'b1 ;
end
end
 
 
// interemediate stage request synchronization flip - flop - this one is prone to metastability
// interemediate stage request synchronization flip - flop - this one is prone to metastability
// and should have setup and hold times disabled during simulation
// and should have setup and hold times disabled during simulation
synchronizer_flop #(1, 0) req_sync
pci_synchronizer_flop #(1, 0) req_sync
(
(
    .data_in        (req_req_pending),
    .data_in        (req_req_pending),
    .clk_out        (comp_clk_in),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_req_pending),
    .sync_data_out  (sync_comp_req_pending),
    .async_reset    (reset_in)
    .async_reset    (reset_in)
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end
end
 
 
assign comp_comp_pending_out = comp_comp_pending ;
assign comp_comp_pending_out = comp_comp_pending ;
 
 
// interemediate stage completion synchronization flip - flop - this one is prone to metastability
// interemediate stage completion synchronization flip - flop - this one is prone to metastability
synchronizer_flop #(1, 0) comp_sync
pci_synchronizer_flop #(1, 0) comp_sync
(
(
    .data_in        (comp_comp_pending),
    .data_in        (comp_comp_pending),
    .clk_out        (req_clk_in),
    .clk_out        (req_clk_in),
    .sync_data_out  (sync_req_comp_pending),
    .sync_data_out  (sync_req_comp_pending),
    .async_reset    (reset_in)
    .async_reset    (reset_in)
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    else
    else
    if ( done_in || comp_cycle_count[16] )
    if ( done_in || comp_cycle_count[16] )
        req_done_reg <= #`FF_DELAY 1'b1 ;
        req_done_reg <= #`FF_DELAY 1'b1 ;
end
end
 
 
synchronizer_flop  #(1, 0) done_sync
pci_synchronizer_flop  #(1, 0) done_sync
(
(
    .data_in        (req_done_reg),
    .data_in        (req_done_reg),
    .clk_out        (comp_clk_in),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_done),
    .sync_data_out  (sync_comp_done),
    .async_reset    (reset_in)
    .async_reset    (reset_in)
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    if ( retry_expired_in && comp_req_pending)
    if ( retry_expired_in && comp_req_pending)
        comp_rty_exp_reg <= #`FF_DELAY 1'b1 ;
        comp_rty_exp_reg <= #`FF_DELAY 1'b1 ;
end
end
 
 
// interemediate stage retry expired synchronization flip - flop - this one is prone to metastability
// interemediate stage retry expired synchronization flip - flop - this one is prone to metastability
synchronizer_flop #(1, 0) rty_exp_sync
pci_synchronizer_flop #(1, 0) rty_exp_sync
(
(
    .data_in        (comp_rty_exp_reg),
    .data_in        (comp_rty_exp_reg),
    .clk_out        (req_clk_in),
    .clk_out        (req_clk_in),
    .sync_data_out  (sync_req_rty_exp),
    .sync_data_out  (sync_req_rty_exp),
    .async_reset    (reset_in)
    .async_reset    (reset_in)
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        req_rty_exp_clr <= #`FF_DELAY 1'b0 ;
        req_rty_exp_clr <= #`FF_DELAY 1'b0 ;
    else
    else
        req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
        req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
end
end
 
 
synchronizer_flop #(1, 0) rty_exp_back_prop_sync
pci_synchronizer_flop #(1, 0) rty_exp_back_prop_sync
(
(
    .data_in        (req_rty_exp_reg && req_rty_exp_clr),
    .data_in        (req_rty_exp_reg && req_rty_exp_clr),
    .clk_out        (comp_clk_in),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_rty_exp_clr),
    .sync_data_out  (sync_comp_rty_exp_clr),
    .async_reset    (reset_in)
    .async_reset    (reset_in)

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