URL
https://opencores.org/ocsvn/pci/pci/trunk
[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_master32_sm.v] - Diff between revs 2 and 6
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 6 |
| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
|
|
// New project directory structure
|
|
//
|
//
|
//
|
|
|
// module includes pci master state machine and surrounding logic
|
// module includes pci master state machine and surrounding logic
|
`include "bus_commands.v"
|
`include "bus_commands.v"
|
`include "constants.v"
|
`include "constants.v"
|
|
`include "timescale.v"
|
|
|
module PCI_MASTER32_SM
|
module PCI_MASTER32_SM
|
(
|
(
|
// system inputs
|
// system inputs
|
clk_in,
|
clk_in,
|
reset_in,
|
reset_in,
|
| Line 410... |
Line 415... |
assign retry_out = timeout_termination || (~pci_stop_reg_in && ~pci_devsel_reg_in) ;
|
assign retry_out = timeout_termination || (~pci_stop_reg_in && ~pci_devsel_reg_in) ;
|
|
|
// AD output flip flops' clock enable
|
// AD output flip flops' clock enable
|
// new data is loaded to AD outputs whenever state machine is idle, bus was granted and bus is in idle state or
|
// new data is loaded to AD outputs whenever state machine is idle, bus was granted and bus is in idle state or
|
// when address phase is about to be finished
|
// when address phase is about to be finished
|
wire load_force = (sm_idle && u_have_pci_bus) || (sm_address && do_write) ;
|
wire load_force = (sm_idle && u_have_pci_bus) || sm_address ;
|
|
|
// next data loading is allowed when state machine is in transfer state and operation is a write
|
// next data loading is allowed when state machine is in transfer state and operation is a write
|
wire load_allow = sm_data_phases && do_write ;
|
wire load_allow = sm_data_phases && do_write ;
|
|
|
// actual loading during data phases is done by monitoring critical target response signals - separate module
|
// actual loading during data phases is done by monitoring critical target response signals - separate module
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.