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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_master32_sm.v] - Diff between revs 21 and 73
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Rev 73 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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parameter S_TA_END = 4'h8 ;
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parameter S_TA_END = 4'h8 ;
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// change state - clock enable for sm state register
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// change state - clock enable for sm state register
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wire change_state ;
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wire change_state ;
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// next state for state machine
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// next state for state machine
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reg [4:0] next_state ;
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reg [3:0] next_state ;
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// SM state register
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// SM state register
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reg [4:0] cur_state ;
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reg [3:0] cur_state ;
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// variables for indicating which state state machine is in
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// variables for indicating which state state machine is in
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// this variables are used to reduce logic levels in case of heavily constrained PCI signals
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// this variables are used to reduce logic levels in case of heavily constrained PCI signals
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reg sm_idle ;
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reg sm_idle ;
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reg sm_address ;
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reg sm_address ;
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