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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_master32_sm_if.v] - Diff between revs 21 and 77
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Rev 77 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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/*====================================================================
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/*====================================================================
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Module provides interface between PCI bridge internals and PCI master
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Module provides interface between PCI bridge internals and PCI master
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state machine
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state machine
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====================================================================*/
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====================================================================*/
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module PCI_MASTER32_SM_IF
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module pci_master32_sm_if
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(
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(
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clk_in,
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clk_in,
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reset_in,
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reset_in,
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// interconnect to pci master state machine
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// interconnect to pci master state machine
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