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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_master32_sm_if.v] - Diff between revs 77 and 94

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Rev 77 Rev 94
Line 40... Line 40...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.4  2003/01/27 16:49:31  mihad
 
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
 
//
// Revision 1.3  2002/02/01 15:25:12  mihad
// Revision 1.3  2002/02/01 15:25:12  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
// Repaired a few bugs, updated specification, added test bench files and design document
//
//
// Revision 1.2  2001/10/05 08:14:29  mihad
// Revision 1.2  2001/10/05 08:14:29  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
// Updated all files with inclusion of timescale file for simulation purposes.
Line 425... Line 428...
        read_bound <= #`FF_DELAY 1'b0 ;
        read_bound <= #`FF_DELAY 1'b0 ;
    else if ( read_count_enable )
    else if ( read_count_enable )
        read_bound <= #`FF_DELAY read_bound_comb ;
        read_bound <= #`FF_DELAY read_bound_comb ;
end
end
 
 
 
wire read_count_change_val = read_count_load | read_count_enable ;
 
 
 
wire [(`WBR_ADDR_LENGTH - 1):0] read_count_next = read_count_load ? max_read_count : (read_count - 1'b1) ;
 
 
// down counter with load
// down counter with load
always@(posedge reset_in or posedge clk_in)
always@(posedge reset_in or posedge clk_in)
begin
begin
    if (reset_in)
    if (reset_in)
        read_count <= #`FF_DELAY 0 ;
        read_count <= #`FF_DELAY 0 ;
    else
    else
    if (read_count_load)
/*    if (read_count_load)
        read_count <= #`FF_DELAY max_read_count ;
        read_count <= #`FF_DELAY max_read_count ;
    else
    else
    if (read_count_enable)
    if (read_count_enable)
        read_count <= #`FF_DELAY read_count - 1'b1 ;
        read_count <= #`FF_DELAY read_count - 1'b1 ;
 
*/  if (read_count_change_val)
 
        read_count <= #`FF_DELAY read_count_next ;
end
end
 
 
// flip flop indicating error recovery is in progress
// flip flop indicating error recovery is in progress
reg err_recovery_in ;
reg err_recovery_in ;
always@(posedge reset_in or posedge clk_in)
always@(posedge reset_in or posedge clk_in)

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