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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_pci_tpram.v] - Diff between revs 77 and 111
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| Rev 77 |
Rev 111 |
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Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.7 2002/10/18 03:36:37 tadejm
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// Revision 1.7 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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// Changed wrong signal name scanb_sen into scanb_en.
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//
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//
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// Revision 1.6 2002/10/17 22:51:08 tadejm
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// Revision 1.6 2002/10/17 22:51:08 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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Line 197... |
//
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//
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// Instantiation of ASIC memory:
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// Instantiation of ASIC memory:
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//
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//
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// Artisan Synchronous Double-Port RAM (ra2sh)
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// Artisan Synchronous Double-Port RAM (ra2sh)
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//
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//
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art_hsdp_256x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
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`ifdef PCI_BIST
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art_hsdp_64x40_bist /*#(dw, 1<<aw, aw) */ artisan_sdp
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(
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(
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.qa(do_a),
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.QA(do_a),
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.clka(clk_a),
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.CLKA(clk_a),
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.cena(~ce_a),
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.CENA(~ce_a),
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.wena(~we_a),
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.WENA(~we_a),
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.aa(addr_a),
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.AA(addr_a),
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.da(di_a),
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.DA(di_a),
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.oena(~oe_a),
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.OENA(~oe_a),
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.qb(do_b),
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.QB(do_b),
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.clkb(clk_b),
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.CLKB(clk_b),
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.cenb(~ce_b),
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.CENB(~ce_b),
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.wenb(~we_b),
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.WENB(~we_b),
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.ab(addr_b),
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.AB(addr_b),
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.db(di_b),
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.DB(di_b),
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.oenb(~oe_b)
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.OENB(~oe_b),
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.scanb_rst (scanb_rst),
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.scanb_clk (scanb_clk),
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.scanb_si (scanb_si),
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.scanb_so (scanb_so),
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.scanb_en (scanb_en)
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);
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);
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`else
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art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
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(
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.QA(do_a),
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.CLKA(clk_a),
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.CENA(~ce_a),
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.WENA(~we_a),
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.AA(addr_a),
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.DA(di_a),
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.OENA(~oe_a),
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.QB(do_b),
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.CLKB(clk_b),
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.CENB(~ce_b),
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.WENB(~we_b),
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.AB(addr_b),
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.DB(di_b),
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.OENB(~oe_b)
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);
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`endif
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`endif
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`endif
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`ifdef AVANT_ATP
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`ifdef AVANT_ATP
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`define PCI_PCI_RAM_SELECTED
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`define PCI_PCI_RAM_SELECTED
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//
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//
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