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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_pcir_fifo_control.v] - Diff between revs 104 and 111

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_pcir_fifo_control.v] - Diff between revs 104 and 111

Rev 104	Rev 111
Line 40...	Line 40...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2003/07/29 08:20:11 mihad`
	`// Found and simulated the problem in the synchronization logic.`
	`// Repaired the synchronization logic in the FIFOs.`
	`//`
`// Revision 1.2 2003/03/26 13:16:18 mihad`	`// Revision 1.2 2003/03/26 13:16:18 mihad`
`// Added the reset value parameter to the synchronizer flop module.`	`// Added the reset value parameter to the synchronizer flop module.`
`// Added resets to all synchronizer flop instances.`	`// Added resets to all synchronizer flop instances.`
`// Repaired initial sync value in fifos.`	`// Repaired initial sync value in fifos.`
`//`	`//`
Line 279...	Line 283...
`Gray coded read address pointer is synchronized to write clock domain and compared to Gray coded next write address.`	`Gray coded read address pointer is synchronized to write clock domain and compared to Gray coded next write address.`
`If they are equal, fifo is full.`	`If they are equal, fifo is full.`
`--------------------------------------------------------------------------------------------------------------------------------*/`	`--------------------------------------------------------------------------------------------------------------------------------*/`
`wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_addr ;`	`wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_addr ;`
`reg [(ADDR_LENGTH - 1):0] wclk_rgrey_addr ;`	`reg [(ADDR_LENGTH - 1):0] wclk_rgrey_addr ;`
`synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_addr`	`pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_addr`
`(`	`(`
`.data_in (rgrey_addr),`	`.data_in (rgrey_addr),`
`.clk_out (wclock_in),`	`.clk_out (wclock_in),`
`.sync_data_out (wclk_sync_rgrey_addr),`	`.sync_data_out (wclk_sync_rgrey_addr),`
`.async_reset (clear)`	`.async_reset (clear)`
Line 305...	Line 309...
`If they are equal, fifo is empty. Synchronized write pointer is also compared to Gray coded next read address. If these two are`	`If they are equal, fifo is empty. Synchronized write pointer is also compared to Gray coded next read address. If these two are`
`equal, fifo is almost empty.`	`equal, fifo is almost empty.`
`--------------------------------------------------------------------------------------------------------------------------------*/`	`--------------------------------------------------------------------------------------------------------------------------------*/`
`wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;`	`wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;`
`reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;`	`reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;`
`synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr`	`pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr`
`(`	`(`
`.data_in (wgrey_addr),`	`.data_in (wgrey_addr),`
`.clk_out (rclock_in),`	`.clk_out (rclock_in),`
`.sync_data_out (rclk_sync_wgrey_addr),`	`.sync_data_out (rclk_sync_wgrey_addr),`
`.async_reset (clear)`	`.async_reset (clear)`